Design Verification Manager

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

About the Role

We are looking for a DV manager to drive verification strategy and technical leadership for image sensor-based SoC programs. The candidate will own SoC-level verification architecture end-to-end, set methodology direction across IP and subsystem teams, and act as the primary technical authority for verification sign-off on imaging SoCs, partnering closely with architecture, design, and software teams from concept through tape-out.

Key Responsibilities

- Define and own the overall SoC verification strategy, architecture, and closure plan for image sensor-based SoC programs.

- Drive verification planning across IP, subsystem, and full-chip levels, ensuring coherent coverage and sign-off criteria.

- Provide technical leadership across multiple verification teams, setting direction on methodology, tooling, and reuse strategy (UVM, formal, emulation/FPGA prototyping as applicable).

- Review and approve verification plans, testbench architectures, and coverage models for critical IPs and subsystems (e.g., image sensor interface, ISP pipeline, MIPI/I3C connectivity, security/crypto blocks).

- Drive SoC-level integration verification - power-up sequences, clocking/reset, interconnect, low-power modes, and cross-IP interactions.

- Champion the use of formal verification for control-logic, FSM, and connectivity verification, and identify where formal can accelerate closure or replace simulation effort.

- Own escalation and resolution of critical verification issues, including specification ambiguities, cross-team dependencies, and schedule-critical bugs.

- Represent verification in program-level reviews, providing risk assessment, closure confidence, and sign-off readiness to senior management and stakeholders.

- Drive root-cause analysis for any post-silicon issues traced to verification gaps, and feed learnings back into methodology and coverage models.

- Mentor and develop senior and mid-level verification engineers; build technical depth and succession within the team.

- Evaluate and drive adoption of new verification tools, flows, and AI-assisted verification techniques to improve productivity and quality.

- Collaborate with external IP/VIP vendors and EDA partners to resolve tool and methodology issues.

Required Skills

- Bachelor's/master's degree in Electronics, Electrical, or Computer Engineering (VLSI specialization preferred).

- 12+ years of experience in digital design/SoC verification, including demonstrated ownership of full-chip or SoC-level verification sign-off.

- Deep expertise in SystemVerilog and UVM methodology, including testbench architecture at IP and SoC level.

- Strong background in functional coverage, code coverage, and assertion-based verification (SVA), with the ability to define SoC-level coverage and closure criteria.

- Hands-on and architectural experience with formal verification tools and methodology (e.g., JasperGold) for FSM, connectivity, and control-path verification.

- Strong understanding of image sensor interfaces and imaging SoC architecture (e.g., MIPI CSI, sensor control protocols such as I3C/I2C, ISP pipelines).

- Proven experience driving SoC-level integration verification: clocking, reset, power domains, low-power verification, and interconnect/fabric verification.

- Strong scripting and automation skills (Python, Perl, or TCL) and experience with regression/CI infrastructure at scale.

- Demonstrated ability to lead cross-functional technical discussions and drive alignment across design, architecture, DFT, and software teams.

- Expertise in Gate-Level Simulation with timing annotation (SDF) , including efficient debugging of timing-related failures.

- Exposure to AI/ML-assisted verification techniques (e.g., test generation, debug automation, coverage analysis) to improve verification productivity and efficiency.

Preferred / Good to Have

- Experience with emulation or FPGA-based prototyping for SoC-level verification.

- Familiarity with security/crypto IP verification in an SoC context.

- Experience with low-power verification (UPF/CPF) at SoC level.

- Prior experience defining or contributing to verification methodology standards/guidelines across an organization.

- Experience working directly with EDA vendors (e.g., Cadence, Synopsys) on tool evaluation and escalations.

- Experience in an automotive-qualified or safety-critical (ISO 26262) SoC verification environment.

Soft Skills

- Strong technical leadership with the ability to set direction and influence without direct authority across teams.

- Excellent judgment in balancing schedule, risk, and verification thoroughness for sign-off decisions.

- Strong communication skills - able to translate technical risk into clear, actionable input for senior management.

- Structured, logical approach to problem decomposition and root-cause analysis on complex, ambiguous issues.

- Passion for mentoring and building technical capability within the team.

- Comfortable operating in a fast-paced, cross-functional, globally distributed program environment.

- Ownership mindset with the ability to work independently and drive closure under deadlines.

- Collaborative approach to working with design, architecture, and cross-functional teams.

- Exposure to AI/ML assisted verification techniques to improve verification productivity and efficiency.

What We Offer

- A high-impact technical leadership role shaping verification strategy for next-generation image sensor SoCs.

- Direct influence over methodology, tooling, and technical direction across the verification organization.

- Opportunity to work at the intersection of imaging, connectivity, and security IP verification.

- Mentorship and people-development opportunities as a manager

- Collaborative environment with global design, architecture, and EDA partner teams.

- A technical leadership track with visibility into IP-level and subsystem-level verification strategy.

- Opportunity to shape verification methodology, including formal and protocol verification practices.

- Exposure to advanced verification domains including formal verification and next-generation Security IP and systems.

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

To discover more, visit st.com/careers.