{"id":968127,"url":"https://alion.io/job/stalentos-sr-sram-layout-design-engineer-supporting-nvidia","title":"Sr. SRAM Layout Design Engineer supporting Nvidia","company":{"id":717076,"name":"Stalentos","domain":"stalentos.com","url":"https://alion.io/company/stalentos","size_band":null,"is_staffing_agency":false,"employer_type":"staffing","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":95,"open_postings":6,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":124,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":110,"max":120,"currency":"USD","period":"hour","gross":null,"usd_annual":240000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false}],"status":"live","first_seen_at":"2026-09-16T14:24:56Z","employer_posted_date":"2026-09-16","last_verified_at":"2026-11-09T18:46:58Z","board_verified":true,"closed_at":null,"days_open":54,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":53},"description":"Sustainable Talent is partnering with NVIDIA, a global leader that has been transforming computer graphics, PC gaming, and accelerated computing for over 25 years. We are looking for a Senior SRAM Layout Design Engineer to support our client's team onsite in Santa Clara, CA. \nThis is a full-time (W-2) contract role. We offer competitive pay $110/hr - $120/hr based on factors like experience, education, location, etc. and provide full benefits, PTO, and amazing company culture!\nWhat you'll do:\nManage the complete custom layout process for SRAM (Static Random-Access Memory) bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.\nDevelop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.\nCarry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.\nSupport EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tape out.\nCollaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.\nCollaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.\nImplement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.\nCollaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.\nReview layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.\nKey required skills:\nHave a BSEE or equivalent experience\n10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.\nHands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.\nSolid grasp of SRAM and memory layout principles.\nExtensive experience in Cadence Virtuoso applied to custom layout creation and assessment.\nExtensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.\nExperience with floor planning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.\nDirect familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.\nAbility to work effectively with circuit build, physical build, integration, CAD, and foundry teams.\nClear communication, strong ownership, good judgment, and the ability to mentor other engineers.\nKnowledge of layout automation or AI tools is a definite plus.\nSustainable Talent is a M/F+, disabled, and veteran equal employment opportunity and affirmative action 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