{"id":3327150,"url":"https://alion.io/job/sykatiya-technology-dft-design-engineer-asicsoc","title":"DFT Design Engineer - ASIC/SoC","company":{"id":3800660,"name":"Sykatiya Technology","domain":"sykatiya.com","url":"https://alion.io/company/sykatiya-technology","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India","Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":15000,"max_usd":34000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":843},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-27T09:44:22Z","employer_posted_date":null,"last_verified_at":"2026-10-27T09:44:22Z","board_verified":false,"closed_at":null,"days_open":2,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":2},"description":"Job Description : \n\nJob Title : DFT Engineer\n\nExperience : 3 - 8 Years\n\nLocation : Bangalore / Hyderabad\n\nAbout the Role : \n\nWe are seeking skilled Design for Testability (DFT) Engineers to join our ASIC/SoC design team. The ideal candidate will have hands-on experience in DFT implementation, ATPG pattern generation, and test architecture development for complex SoC designs. The role involves collaborating with RTL Design, Physical Design, Verification, and Product Engineering teams to ensure high test coverage, improved test quality, and efficient silicon testing.\n\nKey Responsibilities : \n\n- Develop and implement DFT strategies for complex ASIC/SoC designs.\n\n- Perform MBIST planning, architecture definition, and insertion.\n\n- Execute scan architecture planning, scan insertion, and scan-chain configuration.\n\n- Implement test compression and wrapper insertion for improved test efficiency.\n\n- Generate ATPG patterns and perform ATPG simulations and pattern validation.\n\n- Handle both flat and hierarchical SoC designs, ensuring effective DFT integration.\n\n- Work on JTAG implementation, IEEE 1149.1, and boundary scan architecture.\n\n- Create and validate STA constraints for various DFT modes, including shift, capture, and test operations.\n\n- Analyze DFT rule-checking (DRC) violations and resolve testability issues.\n\n- Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.\n\n- Support timing, coverage, and test-quality optimization throughout the design cycle.\n\n- Assist with post-silicon testing, silicon bring-up, and debugging of DFT-related issues.\n\nRequired Skills : \n\n- 3 - 8 years of hands-on experience in DFT implementation and ATPG activities.\n\n- Strong knowledge of MBIST, scan insertion, scan compression, and wrapper insertion.\n\n- Experience in ATPG pattern generation, simulation, and fault coverage analysis.\n\n- Proficiency in handling flat and hierarchical SoC designs.\n\n- Good understanding of JTAG, boundary scan, and DFT architecture.\n\n- Experience in creating STA constraints for DFT modes.\n\n- Knowledge of DFT rule checks, scan-chain debugging, and test coverage improvement.\n\n- Familiarity with industry-standard DFT and ATPG tools.\n\n- Strong problem-solving skills and the ability to collaborate across design teams.\nSkills\nDFT, VLSI, ASIC, SoC, RTL Design, Physical Design, Verification, MBIST, Static Timing Analysis","description_format":"text","description_chars":2394,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Software Testing & QA","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-27T10:32:30Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":1,"expected_fill_days":24,"reasons":["seen:1","win:early"],"computed_at":"2026-10-29T05:49:05Z"},"pay":null,"html_url":"https://alion.io/job/sykatiya-technology-dft-design-engineer-asicsoc","json_url":"https://alion.io/job/sykatiya-technology-dft-design-engineer-asicsoc.json","meta":{"generated_at":"2026-10-29T12:24:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18602,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3800660},"rest":"https://alion.io/mcp/rest/get_company?id=3800660"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsykatiya-technology-dft-design-engineer-asicsoc"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsykatiya-technology-dft-design-engineer-asicsoc"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsykatiya-technology-dft-design-engineer-asicsoc"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/sykatiya-technology-dft-design-engineer-asicsoc\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsykatiya-technology-dft-design-engineer-asicsoc"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3327150}},{"tool":"search_jobs","arguments":{"company":"sykatiya.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3327150},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}