{"id":3182136,"url":"https://alion.io/job/synchron-senior-rd-engineer-electrical-fpga-design","title":"Senior R&D Engineer, Electrical & FPGA Design","company":{"id":63210,"name":"Synchron","domain":"synchron.com","url":"https://alion.io/company/synchron","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"ADP","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Diego, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":180000,"currency":"USD","period":"year","gross":null,"usd_annual":180000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Altium Designer","optional":false},{"name":"Design Controls","optional":false},{"name":"Embedded C","optional":false},{"name":"FMEA","optional":false},{"name":"IEC 60601","optional":false},{"name":"IEC 62304","optional":false},{"name":"Ion Implantation","optional":false},{"name":"ISO 14971","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verification & Validation","optional":false},{"name":"VHDL","optional":false},{"name":"C","optional":true},{"name":"DO-254","optional":true},{"name":"FDA 510(k)","optional":true},{"name":"RTOS","optional":true}],"status":"live","first_seen_at":"2026-10-23T21:53:50Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-26T00:55:06Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"TITLE\nSr. R&D Engineer, Electrical & FPGA Design\nDATE\nOctober 2026\nWORK LOCATION\nIn-Office 5x/week in San Diego\nBASE SALARY RANGE\n$140,000 - $180,000/year\nAbout the Role\nWe are seeking a Senior R&D Electrical Engineer to own the electrical and programmable-logic design of Synchron's next-generation implantable electronics, from concept through design verification. The core of the role is defining and developing the HDL for the implant's low-power FPGA: supervisory logic for device health, status, and control, and the implant side of a high-speed serial link to distributed sensing electronics, defined from interface specifications with external silicon partners and proven in FPGA emulation ahead of hardware. The role also owns the surrounding electrical architecture - custom silicon integration, inductive charging and RF telemetry, and PCB/flex design - and carries a safety mandate: detectable faults, redundant monitoring, and defined safe states within a medical device design-controls framework.\nFirmware is owned by a dedicated engineer; this role reviews, debugs, or contributes to firmware and test software as the program needs. This is a hands-on, technically deep role: equally comfortable reviewing RTL and schematics as defining system-level architecture.\nKey Responsibilities\nFPGA / HDL Design\nArchitect and develop synthesizable HDL (VHDL or SystemVerilog) for a low-power FPGA serving as the implant's health, status, control, and communications controller; select the FPGA family and configuration approach against power, size, I/O, and configuration-integrity constraints\nImplement supervisory functions: power sequencing, voltage/current/temperature monitoring, watchdogs, fault detection and latching, status reporting to the host MCU, and transition to defined safe states\nOwn timing closure, clock-domain crossing, and low-power clocking; develop self-checking testbenches and simulation regressions appropriate to safety-relevant logic\nDefine and verify the FPGA/MCU interface (SPI, register map); own FPGA bring-up, diagnostics, and configuration/update strategy\nHigh-Speed Sensor Communications Link\nDefine and implement the implant side of the serial link to distributed sensing electronics: clock generation and distribution, line driver/receiver scheme (including emulated-LVDS I/O), framing, synchronization, error detection, and recovery\nDerive and maintain link and timing budgets (jitter, skew, channel loss) and reconcile them with partner models\nBuild bench models and FPGA emulation of the link, integrating partner-supplied RTL, to retire risk before final hardware\nSafety & Redundant Systems\nDesign control and monitoring logic so single faults are detected and contained: redundant or diverse monitors, FPGA/MCU cross-checks, independent shutdown paths, and fail-safe defaults on loss of clock, power, or communication\nDefine safe-state behavior and entry/exit conditions; perform FMEA / fault-tree analysis and trace risk controls to design inputs and verification per ISO 14971\nApply configuration-integrity and single-event-upset mitigations (CRC, readback, redundancy) for chronically implanted programmable logic\nElectrical Architecture, Power & RF\nOwn the implant's electrical architecture and lead schematic design, component selection, and simulation for ultra-low-power implantable electronics\nDesign and characterize the inductive charging link: receive coil geometry and placement, resonant tuning, rectification and regulation, alignment and load tolerance, and tissue heating limits\nOptimize the wireless telemetry link (custom RF, BLE, or inductive) under tissue constraints, including antenna selection, matching, and integration within the hermetic enclosure and header\nEstablish power budgets and duty-cycling strategies that balance data throughput against implant longevity\nPCB/Flex, Verification & Design Controls\nLead design of miniaturized, high-density PCB and flex-rigid assemblies in Altium Designer, including layout review, signal integrity, and DFM at implant scale\nDefine and execute electrical and FPGA verification plans; lead bench, environmental, and EMC/EMI testing; own failure analysis and design-for-reliability practices\nServe as electrical and programmable-logic lead within design controls (IEC 60601-1, IEC 62304, ISO 14708); author design inputs, risk analyses, and V&V protocols with traceability from requirements to RTL and test; support regulatory submissions\nCollaboration\nPartner with firmware, silicon, mechanical, and systems engineers to co-optimize the implant; review firmware and test-software changes touching the electrical and FPGA interfaces and step in on cross-domain debug\nWork with contract manufacturers and test houses to transfer designs into production\nRequired Qualifications\nBachelor's degree in electrical engineering, computer engineering, or a related discipline\n8+ years in mixed-signal hardware design for miniaturized, high-reliability electronic systems\n5+ years of hands-on FPGA development: synthesizable VHDL or SystemVerilog, clock-domain crossing and timing closure, and simulation-based verification, on low-power FPGA families\nWorking knowledge of serial interface design: source-synchronous or CDR schemes, LVDS/CML signaling, framing and error detection, SPI/I2C, and register-map design\nDemonstrated design of safety-relevant or fault-tolerant digital systems: watchdogs, redundant monitors, fail-safe defaults, fault detection and isolation\nHands-on experience with inductive power transfer or near-field wireless charging, or equivalent resonant/magnetics design\nStrong high-density PCB and flex-circuit design experience with proficiency in Altium Designer; SPICE-class simulation and signal-integrity analysis\nAbility to read, debug, and review embedded C firmware and test software, and contribute when needed\nExperience bringing electronic subsystems from prototype through design verification into production\nPreferred Qualifications\nActive implantable medical device experience (e.g., neurostimulators, cochlear implants, cardiac rhythm devices)\nCustom silicon integration or co-design, including specification development, emulation of partner RTL on FPGA, and bring-up\nFunctional-safety or high-integrity design standards (IEC 60601-1 PEMS, IEC 62304, IEC 61508 / ISO 26262 concepts, DO-254-style assurance)\nAntenna or RF front-end design for implantable or body-worn devices, including EM simulation (HFSS, CST, or COMSOL)\nCoil design and EM/thermal modeling for inductive links, including MRI-compatibility constraints on magnetic materials\nLow-noise neural or bioelectric front-end design; embedded firmware development on wireless SoCs with an RTOS and BLE\nFamiliarity with ISO 14708, IEC 60601, and FDA guidance for implantable electronics; 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