{"id":1311336,"url":"https://alion.io/job/synopsys-18733-asic-digital-design-principal-verification-engineer","title":"18733 - ASIC Digital Design, Principal Verification Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":81000,"max_usd":147000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-23T09:43:04Z","board_verified":true,"closed_at":null,"days_open":26,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":26},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building verification environments for complex digital designs where mistakes show up as silicon respins or customer escalations. The difference between a PHY that passes regression and one that works in production is something you understand deeply, and it shapes how you write testplans, model coverage, and design infrastructure.\nThe testbenches you build are meant to last. You have inherited enough unmaintainable code to know what matters when a project needs to scale across multiple product generations. Working across distributed teams is something you have done enough times to know when to align closely with architects on protocol details and when to just push forward on debug with RTL and firmware engineers in other time zones.\nTechnical reviews matter to you because that is where you can catch verification risks before they become schedule problems. At Synopsys, you will work on memory interface IP with a team that takes verification seriously as its own discipline, not just a gate before tapeout.\nWhat You'll Be Doing\nDevelop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs \nBuild and maintain testbench infrastructure in SystemVerilog and UVM that supports complex verification scenarios across multiple product generations \nCreate test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements \nDebug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools \nParticipate in technical reviews with architecture and implementation teams to influence design decisions from a verification perspective \nResearch and evaluate emerging technologies in virtual prototyping and emulation to improve team efficiency, throughput, and quality \nMentor junior engineers on testbench design, debugging techniques, and verification methodology while collaborating with other principal-level engineers on verification strategy\nThe Impact You Will Have\nYour testplans and coverage models will define the quality bar for memory interface IP that powers next-generation products across the industry \nThe testbench infrastructure you build will accelerate verification cycles and enable the team to scale as new product lines come online \nYour debugging expertise will catch critical issues before they reach customers, protecting both product schedules and Synopsys reputation \nTechnical reviews you contribute to will shape architecture decisions early, preventing costly verification bottlenecks downstream \nNew verification technologies you evaluate and adopt will directly improve team productivity and reduce verification time \nEngineers you mentor will carry forward the verification rigor and problem-solving approach that makes complex IP actually work \nYour work with customers (on simulation debug or post-silicon bring-up debug) will strengthen their confidence in our IP and inform future product roadmaps \nWhat You'll Need\nBSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years \nDeep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments \nStrong command of simulation tools, waveform debuggers, and the ability to trace issues across multiple abstraction layers \nSolid understanding of C and experience with software/hardware co-simulation \nExperience with assertion-based verification, coverage analysis, and protocol-oriented performance debug \nComfort working in Linux environments with scripting for regression systems, build automation, and source control workflows \nExperience with virtual prototyping or emulation platforms is a strong plus, as is knowledge of LPDDR5/5X and LPDDR6 or other memory interface standards \nWho You Are\nYou can read a functional spec and immediately start sketching out the test scenarios that will stress the design in ways the architects did not anticipate \nYou work effectively across distributed teams without needing constant check-ins, you know when to sync up and when to just make progress \nYou bring a point of view to design reviews and you are not afraid to flag a verification risk even if it means pushing back on a schedule \nYou balance thoroughness with pragmatism, you know when a testbench needs another week of work and when it is good enough to start finding real bugs \nYou explain complex verification trade-offs clearly enough that an architect or project manager understands the risk without needing a deep dive into UVM internals \nThe Team You'll Be Part Of\nYou will join the IP Group in Ottawa, a team focused on developing interface IP solutions for memory interfaces. The team is international, with members collaborating across multiple time zones to deliver IP that ships into high-volume products. You will work alongside other principal-level verification engineers, contributing to verification strategy while also building and executing on testplans. The group values technical depth, rigorous methodology, and the kind of verification work that actually prevents customer issues rather than just checking compliance boxes.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":6380,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 178 · green card filings: 177","filings_12m":178,"filings_prev_12m":208,"green_card_filings_12m":177,"median_offered_wage_usd":157472,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":61},{"country":"GB","licensed_sponsor":true,"evidence":"Licensed UK visa sponsor (Skilled Worker)","filings_12m":null,"filings_prev_12m":null,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Skilled Worker","cap_exempt":false,"checked_at":"2026-10-23T06:21:00+00:00","sources":["UK Home Office: register of licensed sponsors (workers)"],"filings_for_role_12m":0}],"liveness":{"score":30,"band":"fade","label":"Fading","p_open":1,"p_active":0.656,"p_room":0.45,"age_days":26,"expected_fill_days":15,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-18733-asic-digital-design-principal-verification-engineer","json_url":"https://alion.io/job/synopsys-18733-asic-digital-design-principal-verification-engineer.json","meta":{"generated_at":"2026-10-23T13:15:08Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19742,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-18733-asic-digital-design-principal-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-18733-asic-digital-design-principal-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-18733-asic-digital-design-principal-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-18733-asic-digital-design-principal-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-18733-asic-digital-design-principal-verification-engineer"}]}