{"id":1903077,"url":"https://alion.io/job/synopsys-18917-rd-engineering-sr-staff-engineer","title":"18917 - R&D Engineering, Sr Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":85,"ghost_share":0.035,"stale_share":0,"repost_share":0.176,"time_to_fill_p50_days":11,"computed_at":"2026-10-08T05:49:30Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":74000,"max_usd":129000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":62},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Linux","optional":false},{"name":"Windows","optional":false}],"status":"live","first_seen_at":"2026-10-05T11:58:46Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-08T20:57:42Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nHaving spent a decade or more working at the intersection of silicon, packaging, and board design, you know where good architectures succeed and where they fail. Evaluating package architectures, reviewing power delivery networks and bump maps, and turning SI/PI and EM analysis into sound engineering decisions are all part of your toolkit. When faced with ambiguity, you know how to focus on the issues that matter and keep complex programmes moving forward.\nAt Synopsys, you'll lead package design for advanced IP test chips at the forefront of performance. Working with tools such as Ansys HFSS and collaborating across engineering teams, you'll help shape the technologies that enable the next generation of semiconductor products. Just as importantly, you'll bring the confidence to challenge assumptions, ask the right questions, and drive decisions that move the design forward.\nWhat You'll Be Doing\nLead four to six test-chip package designs per year from requirements definition through final delivery, coordinating across internal teams, customers, and external partners\nDefine package requirements early in the design cycle, including bump maps, ball maps, and layer stack-up decisions that optimize signal integrity and power integrity performance\nPerform hands-on physical design and layout of advanced package substrates using industry-standard EDA tools\nExtract electrical models from substrate designs using 3D EM simulation tools like Ansys HFSS, and analyze them against SI and PI requirements to validate performance\nGuide customers through package architecture evaluations and tradeoff analysis to identify implementation options that work for Synopsys IP\nResolve complex package design and integration issues by developing technically sound solutions that balance electrical performance, manufacturability, and cost\nProvide regular project updates to management covering progress, technical risks, dependencies, mitigation plans, and decisions that need escalation\nThe Impact You Will Have\nEnable successful tape-outs of Synopsys IP test-chips by ensuring package designs meet electrical and physical performance requirements from day one\nReduce design iteration cycles and avoid costly respins by catching signal integrity and power integrity issues early through rigorous modeling and analysis\nExpand the range of package solutions available to Synopsys customers by evaluating new architectures and proving out their viability for high-performance IP\nStrengthen customer relationships by providing expert guidance on package design decisions that directly affect their product success\nImprove design quality and efficiency across the team by establishing best practices for substrate layout, model extraction, and SI/PI validation\nAccelerate time-to-market for Synopsys IP by coordinating design phases, technical reviews, and handoffs that keep projects moving without surprises\nInfluence cross-functional business-unit projects by representing the package design perspective in technical decisions that affect multiple teams\nWhat You'll Need\n10+ years of hands-on experience in semiconductor package design, package substrate layout, electrical modeling, or closely related work\nAdvanced knowledge of circuit theory and transmission line behavior, with the ability to apply it to high-speed package interconnect design and analysis\nDemonstrated experience building, validating, and interpreting 3D electromagnetic models using Ansys HFSS or comparable simulation tools\nStrong written and verbal communication skills in English, with the ability to explain complex technical tradeoffs to customers, partners, and cross-functional teams\nWorking knowledge of Windows and Linux environments used for engineering design and analysis workflows\nBachelor's degree in electrical engineering, electronics engineering, or equivalent field\nExperience with advanced packaging technologies such as 2.5D interposers, fan-out wafer-level packaging, or chiplet integration is a plus\nThe Team You'll Be Part Of\nYou will work with a highly skilled and supportive global team focused on ensuring Synopsys IP test-chip packages meet electrical and physical performance requirements. Your recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":5382,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-05T11:58:46Z"}],"visa":[],"liveness":{"score":87,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.869,"p_room":1,"age_days":2,"expected_fill_days":11,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-10-08T05:49:30Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-18917-rd-engineering-sr-staff-engineer","json_url":"https://alion.io/job/synopsys-18917-rd-engineering-sr-staff-engineer.json","meta":{"generated_at":"2026-10-09T00:43:44Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1047,"day_limit":5000,"remaining_today":3953,"minute_limit":60,"resets_at":"2026-10-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-18917-rd-engineering-sr-staff-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-18917-rd-engineering-sr-staff-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-18917-rd-engineering-sr-staff-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-18917-rd-engineering-sr-staff-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-18917-rd-engineering-sr-staff-engineer"}]}