{"id":2460890,"url":"https://alion.io/job/synopsys-analog-design-sr-engineer-18613","title":"Analog Design, Sr Engineer - 18613","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":85,"ghost_share":0.035,"stale_share":0,"repost_share":0.176,"time_to_fill_p50_days":12,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Pavia, Italy"],"countries":["IT"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":44000,"max_usd":72000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":67},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bash","optional":false},{"name":"C++","optional":false},{"name":"Linux","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-13T17:19:13Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-15T05:16:49Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent your academic career and early professional years building an understanding on different aspects of either analog or digital design and have curiosity of how high-speed communication systems actually work, not just in theory but in the messy reality where channel loss, jitter, non linearities, DSP sizing, LMS convergence and impedance mismatches determine whether a link closes or fails. You strive for holistic understanding of complex systems and you believe the way to create at optimized product is to capture the interaction between analog circuits, digital logic, and algorithms in a single coherent simulation environment.\nCollaboration comes naturally to you.\nWhen a model behaves differently than the circuit description suggests you hunt for the truth. You sit with the analog designer who owns the amplifier block, understand the frequency response trade-offs, and update your MATLAB representation until it reflects reality. You are comfortable presenting technical results in gate reviews and defending your sign-off decisions when someone questions your assumptions.\nYou care about closing the loop between simulation and silicon. When lab measurements do not match your predictions, you treat it as a puzzle and get into the lab to solve it. At Synopsys, you will work on leading edge SerDes IP that powers PCIe and Ethernet interfaces across the semiconductor industry.\nWhat You'll Be Doing\nBuild and update MATLAB models of SerDes analog and DSP blocks in cooperation with the system architect, translating circuit designs into accurate system-level representations\nOwn system sign-off and performance evaluation for SerDes products, presenting results in gate reviews and carrying the outcome into successful product releases\nChallenge and update models to close simulation-to-silicon correlation, working directly with the post-silicon validation team to understand lab data and refine predictions\nWork with analog and digital engineers to assess how block and algorithm choices affect link quality and system performance across the signal chain\nCheck algorithm behavior against Ethernet and PCIe specifications, ensuring product operation aligns with compliance requirements\nDevelop new algorithms required for product operation or performance improvements, translating system-level needs into implementable solutions\nScript and automate simulation runs, including AI-assisted flows, to improve efficiency and enable faster design iteration\nSupport lab-data analysis and debug on existing products, helping validation teams understand performance issues and root causes\nThe Impact You Will Have\nEnsure SerDes IP meets performance targets before release, reducing risk of costly silicon respins and delays\nProvide the holistic system view that brings analog, digital, firmware, and validation disciplines into a unified understanding of product performance\nShape next-generation SerDes architectures by identifying performance bottlenecks and optimization opportunities early in the design cycle\nImprove simulation-to-silicon correlation across the product portfolio, making future development cycles faster and more predictable\nEnable successful product releases by catching specification compliance issues and performance gaps before tapeout\nInfluence how high-speed interfaces perform in networking, AI, and data center applications used by customers worldwide\nAct as the technical integration point where contributions from multiple engineering teams are evaluated, validated, and signed off together\nWhat You'll Need\nMasters degree in Electrical Engineering, Electronics Engineering, or a related field\nRelevant experience, such as: internships, thesis work, or early industry experience in communications, circuits, or signal processing is a strong plus\nProficiency in MATLAB or C++ for system modeling, scripting, and automation\nSolid understanding of analog and digital circuit fundamentals, including SerDes architectures, channel loss and equalization, amplifier frequency response, reflections and impedance matching, jitter analysis, and DAC/ADC architectures and performance metrics\nBasic understanding of optical communication systems and photonics\nFluent English, including the ability to present technical topics and answer audience questions clearly\nFamiliarity with Linux and Bash, Python, prior SerDes or communications-modeling projects, or lab measurement experience is a plus\nWho You Are\nYou ask the right questions when a model behaves differently than the circuit description suggests, and you do not move forward until the gap is resolved\nYou are collaborative by instinct, working closely with the system architect and with analog, digital, and algorithm designers to ensure model accuracy\nYou can present system sign-off results in a gate review, explain your methodology, and defend your conclusions when stakeholders challenge your assumptions\nYou are organized and persistent in problem-solving, managing multiple modeling tasks and simulation runs without losing track of details that affect accuracy\nYou communicate clearly across engineering domains, translating between analog circuit behavior, digital implementation constraints, and algorithm performance trade-offs\nYou treat simulation-to-silicon correlation as a puzzle worth solving, diving into lab data with the validation team to understand why predictions and measurements diverge\nThe Team You'll Be Part Of\nYou will join the SerDes system team in Pavia, which develops and maintains the link model for high-speed serial links compliant with the latest PCIe and Ethernet specifications. The team includes system architects and works closely with R&D functions across analog design, digital design, firmware design and validation, and hardware engineering. This team is the ultimate owner of system architecture and performance, ensuring the quality of existing products and shaping next-generation devices. The role sits at the center of the disciplines that build a complex system, with the goal of making sure the pieces work together to deliver the functionality and performance of the whole system.\nRole Details\nLocation: Pavia, Italy\nWorking Model: Hybrid\nExpected Start Date: December 2026\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":7279,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":[],"hiring_locations":[{"name":"Italy","iso":"IT","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-13T17:19:13Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":12,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-analog-design-sr-engineer-18613","json_url":"https://alion.io/job/synopsys-analog-design-sr-engineer-18613.json","meta":{"generated_at":"2026-10-15T08:45:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13198,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-analog-design-sr-engineer-18613"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-analog-design-sr-engineer-18613"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-analog-design-sr-engineer-18613"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-analog-design-sr-engineer-18613\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-analog-design-sr-engineer-18613"}]}