{"id":1311235,"url":"https://alion.io/job/synopsys-applications-engineering-sr-staff-engineer-18510","title":"Applications Engineering, Sr Staff Engineer - 18510","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":110,"ghost_share":0.027,"stale_share":0,"repost_share":0.164,"time_to_fill_p50_days":4,"computed_at":"2026-09-26T05:45:00Z"}},"role":"Backend","role_family":"Backend","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":48000,"max_usd":100000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":8},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T19:50:00Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAlternate Job Titles\nSenior Staff Verification Engineer\nSr Staff Applications Engineer, Simulation & Debug\nPrincipal Application Engineer, VCS/Verdi\nSenior Staff FAE, Verification Solutions\nSr Staff Technical Solutions Engineer, EDA\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in verification, the kind where a missed edge case costs six months and millions of dollars, and you have learned to think like both the designer who built it and the engineer trying to break it. You know that simulation is not just about running tests, it is about understanding why a testbench stalls at 3am, why coverage is stuck at 87%, and what it takes to get a customer from \"this doesn't work\" to \"this is faster than anything we've run before.\"\nYou are comfortable sitting with a customer's verification team, digging into their UVM environment or gate-level timing flow, and walking out with a deployment plan that actually works in their environment, not just in a demo. You do not wait for perfect documentation. You read waveforms, trace through SystemVerilog, script your way around problems, and know when to pull in R&D versus solve it yourself.\nCompetitive benchmarks do not intimidate you. You have run them, you know where VCS wins, and you can explain it in terms that matter to the person signing the contract. You care about the craft. At Synopsys, you will work on verification technology that powers tape-outs across the industry, and the customers you support will remember your name.\nWhat You'll Be Doing\nDrive customer deployments of VCS and Verdi simulation and debug platforms, working directly with design and verification teams to integrate tools into their existing flows\nDiagnose complex technical issues across UVM testbenches, gate-level simulations, low power flows, and timing-aware verification environments\nLead competitive engagements and benchmarking efforts, demonstrating VCS/Verdi performance, capacity, and debug advantages against rival tools\nCollaborate with R&D and product teams to gather customer requirements, reproduce field issues, and influence the product roadmap based on real deployment feedback\nDevelop and optimize automation scripts in Perl, Python, TCL, Shell, and Make to improve customer productivity and streamline verification workflows\nInterface across global teams including product validation, field applications, and customer engineering to propose solutions and drive product improvements\nSupport customers through technical escalations, providing expertise in SystemVerilog, SVA, UVM, low power (UPF), and gate-level simulation methodologies\nThe Impact You Will Have\nEnable customers to close verification faster and reach first-pass silicon success by deploying simulation technology that scales to their toughest designs\nInfluence the VCS and Verdi product roadmap by surfacing real-world customer challenges and competitive gaps that R&D can act on\nWin competitive deals by proving performance, capacity, and debug superiority in head-to-head benchmarks that matter to customer schedules\nAccelerate adoption of advanced features like AI-driven productivity tools, formal integration, and next-gen debug capabilities across your customer base\nReduce time-to-resolution for critical customer issues, turning escalations into deployments and deployments into long-term partnerships\nStrengthen Synopsys' position as the verification platform of choice by making customers successful in ways they can measure and defend internally\nBuild institutional knowledge across the global applications team by documenting solutions, sharing best practices, and mentoring peers on complex verification challenges\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering or equivalent, with 5-12 years of hands-on experience in verification or application engineering\nDeep expertise in simulation technologies, UVM, SystemVerilog Assertions (SVA), and verification methodologies applied to real designs\nStrong command of HDL languages including Verilog, VHDL, and SystemVerilog, with solid understanding of digital design fundamentals\nProven experience with gate-level simulation, timing-aware verification, and low power flows using UPF\nAdvanced scripting ability in Perl, Python, TCL, Shell, and Make, with comfort working in UNIX/Linux environments\nExperience with Synopsys Verdi or similar waveform debug tools is a strong plus, as is knowledge of DPI, C/C++, SystemC, or functional safety standards\nExposure to generative AI technologies or AI-driven EDA workflows is a plus\nWho You Are\nYou can walk into a customer meeting, listen to a verification problem described in half-formed sentences, and walk out with a clear technical plan and next steps\nYou are the person your team pulls in when a customer issue is stuck, not because you know everything, but because you know how to find the answer and who to ask\nYou manage multiple customer engagements at once without dropping threads, and you do not need reminders to follow up or close the loop\nYou push back when a proposed solution does not fit the customer's actual environment, and you are comfortable saying \"that won't work, here's what will\"\nTravel does not faze you, whether it is onsite customer visits, regional workshops, or working across time zones with global R&D and field teams\nYou stay current, not because it is required, but because you are genuinely curious about what is next in verification, AI tooling, and EDA technology\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6603,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":7,"reasons":["conf:9","win:early","comp:brand"],"computed_at":"2026-09-27T05:30:47Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-applications-engineering-sr-staff-engineer-18510","json_url":"https://alion.io/job/synopsys-applications-engineering-sr-staff-engineer-18510.json","meta":{"generated_at":"2026-09-27T05:30:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4836,"day_limit":5000,"remaining_today":164,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}