{"id":3082777,"url":"https://alion.io/job/synopsys-applications-engineering-staff-engineer-19421","title":"Applications Engineering, Staff Engineer - 19421","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Backend","role_family":"Backend","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Agrate Brianza, Italy"],"countries":["IT"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":68000,"max_usd":128000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":11},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"Synopsys VC Formal","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-22T12:44:47Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-25T06:47:37Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in verification, close enough to the tools to know what breaks and close enough to customers to know the right answer depends on what they are actually trying to verify. You have debugged enough RTL and traced enough CDC violations to understand verification is about building confidence the design will work when it ships.\nYou walk into customer meetings, listen to what they are stuck on, and map problems to solutions they can use. When something does not work, you reproduce it and show up with enough context that R&D can fix it. You like bridging product and customer reality. At Synopsys, you will work with semiconductor teams across Europe who depend on verification tools to catch issues that would otherwise cost months in silicon.\nWhat You'll Be Doing\nSupport pre-sales demos, benchmarks, and proof-of-concept work that helps customers evaluate verification solutions\nDeploy and troubleshoot verification tools post-sale, resolving issues with customer engineering teams\nApply expertise in static verification using SpyGlass, formal verification with VC Formal, or dynamic simulation using VCS and UVM\nWork with R&D to communicate customer needs and reproduce issues\nDeliver technical workshops and training on verification technologies\nBuild trusted relationships with engineering and management at semiconductor companies across Italy and Europe\nThe Impact You Will Have\nEnable customers to catch critical design issues earlier, reducing respins and schedule risk\nAccelerate tool deployment by resolving blockers and providing methodology guidance\nInfluence product roadmaps by surfacing customer requirements\nHelp close deals by running evaluations that demonstrate value on customer designs\nReduce support escalations by diagnosing issues and providing R&D with context\nWhat You'll Need\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field\n5+ years in the semiconductor industry at an EDA company or semiconductor design company\nHands-on experience in RTL verification or verification methodology\nStrong knowledge in static verification (SpyGlass), formal verification (VC Formal), or dynamic simulation (VCS, UVM)\nProficiency in Verilog and SystemVerilog\nComfort with Linux and scripting in Tcl, Python, Perl, or shell\nFluent English; Italian language skills are a strong advantage\nWho You Are\nYou listen to a verification problem and walk out with a plan that maps to tool features and methodology changes\nYou reproduce issues and show up with enough detail that problems can be solved\nYou present comfortably to engineers who want depth and managers who want to know if this will work\nYou manage multiple customer engagements without losing track of commitments\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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