{"id":4268639,"url":"https://alion.io/job/synopsys-asic-digital-design-director-19735","title":"ASIC Digital Design, Director - 19735","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agentic Workflows","optional":false},{"name":"AI Agents","optional":false},{"name":"CI/CD","optional":false},{"name":"Model Context Protocol","optional":false},{"name":"Python","optional":false},{"name":"RAG","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-13T17:05:13Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T17:05:13Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nJob Title: - Engineering Director- Subsystem Interoperability & AI-Driven Verification\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent two decades building verification teams and solving the problems that live between IP blocks, where clean interfaces meet messy reality and independently verified components refuse to cooperate. The gap between a Controller that passes all tests and a Controller-PHY-firmware combination that actually works in a customer SoC is where you live, and you have built the instincts to close it.\nYou are technical enough to review a UVM testbench, debug a protocol violation three layers deep, and make the call on whether a coverage hole is real or academic. But you also know that verification at scale is not about heroic debug sessions, it is about building systems that catch problems before they become customer issues. You think in factories, not fire drills.\nWhat excites you now is applying AI to verification work that has resisted automation for years. You see LLMs, agentic workflows, and intelligent orchestration not as buzzwords but as tools that can finally turn interoperability from a bottleneck into a continuously running capability. You are ready to build that capability from the ground up at Synopsys, where the IP portfolio is real, the customer stakes are high, and the technical challenge is exactly the kind you have been preparing for.\nWhat You'll Be Doing\nBuild and lead the Central Interoperability team from scratch, defining its technical strategy, organizational structure, verification methodology, execution model, and success metrics across high-speed interface IPs including UCIe, PCIe, CXL, DDR, HBM, Ethernet, and USB\nOwn end-to-end Controller-PHY interoperability qualification, from UVM environment bring-up and configuration management through verification execution, functional and structural coverage closure, protocol compliance, debug, and generation of customer-ready release evidence\nEstablish an always-on Interop Factory where new Controller, PHY, or firmware releases automatically trigger integration, regression suites, qualification workflows, and evidence generation without manual intervention\nDrive interoperability verification beyond basic connectivity into protocol compliance, stress and error injection scenarios, CDC/RDC checks, timing constraints validation, and implementation readiness across the Controller × PHY × Firmware × VIP × Configuration state space\nMake the factory AI-native by applying LLMs, AI agents, RAG, MCP, and intelligent workflow orchestration to environment generation, test plan development, regression selection, failure clustering, root-cause analysis, debug acceleration, and knowledge reuse across releases\nBuild a continuous learning loop where customer issues feed directly into root-cause analysis, prevention test creation, regression integration, and future release qualification, systematically converting field learning into improved product quality\nPartner across Controller and PHY R&D teams, architecture, VIP development, firmware, methodology, applications engineering, and product management to create one accountable, transparent subsystem-readiness view for every release\nThe Impact You Will Have\nYou will create a new verification capability that shifts interoperability left in the development cycle, reducing subsystem bring-up time for customers and increasing the number of qualified Controller-PHY-firmware configurations available at release\nYou will transform interoperability from a customer integration exercise into a continuously verified product capability, with reusable qualification evidence and clear release gates that reduce field issues and support escalations\nYour factory will establish a scalable blueprint for subsystem verification across the broader Synopsys IP portfolio, creating reusable infrastructure, methodology, and AI-enabled automation that other teams can adopt\nYou will build a team culture that attracts top verification talent, mentors engineers into technical leadership roles, and keeps the organization technically engaged even as it scales\nYou will make AI-assisted verification real and measurable, demonstrating how LLMs and agentic workflows can accelerate debug, improve coverage strategies, and turn tribal knowledge into reusable intelligence\nYou will create predictable, data-driven subsystem readiness visibility for executives and customers, replacing subjective assessments with objective qualification metrics tied to real verification evidence\nYou will reduce the time from IP release to customer-ready subsystem from months to weeks by automating the integration, qualification, and evidence-generation workflows that currently require manual coordination\nWhat You'll Need\n20+ years of semiconductor design and verification experience with significant technical leadership responsibility building and scaling verification teams\nDeep expertise in ASIC, SoC, IP, or subsystem verification using SystemVerilog, UVM, verification planning, functional and code coverage analysis, assertions, regression infrastructure, and complex multi-IP debug\nStrong hands-on experience with high-speed protocols such as UCIe, PCIe, CXL, DDR, HBM, Ethernet, USB, or SerDes, including protocol compliance, Controller-PHY integration, and interoperability challenges\nProven track record integrating independently developed IP blocks and driving complex cross-functional technical programs across R&D, product, and applications teams\nStrong scripting and automation skills using Python, Tcl, or equivalent for building verification infrastructure, regression frameworks, and intelligent workflow orchestration\nExperience with CDC/RDC verification, formal methods, emulation or prototyping platforms, CI/CD for verification, or physical implementation flows is highly desirable\nExposure to LLMs, agentic AI, RAG, MCP, AI-assisted verification or debug tools, or intelligent engineering automation is strongly preferred and will differentiate your application\nWho You Are\nYou can sit in a technical review with verification engineers debugging a CXL protocol failure and walk out with a clear action plan, then turn around and explain the customer-readiness risk to a VP in two sentences without losing the technical nuance\nYou do not wait for perfect alignment across teams to get started, you define the interoperability strategy, build the initial environment, and prove the value before asking for full organizational buy-in\nYou recruit engineers who are better than you at specific things and you create the conditions for them to do their best work, whether that is deep UVM expertise, AI automation, or protocol-level debug\nYou have a point of view on what good verification looks like and you push back when a test plan is too shallow, a coverage model is missing critical scenarios, or a release gate is being bypassed without real justification\nYou are energized by building new capabilities from scratch, not inheriting mature organizations, and you are comfortable with the ambiguity, cross-functional negotiation, and technical problem-solving that comes with that\nYou stay technical, you still read code, review testbenches, understand coverage reports, and debug failures alongside your team, because that is how you earn credibility and make good decisions\nThe Team You'll Be Part Of\nYou will build the Central Subsystem Interoperability team from the ground up, establishing its charter, hiring its engineers, and defining its relationship to Controller R&D, PHY R&D, VIP, firmware, and product teams across Synopsys. This is a new capability being created to transform how independently developed IP becomes qualified, customer-ready subsystems. You will report into senior engineering leadership and work closely with architecture, methodology, and product management to establish the vision, execution model, and success metrics for this organization. Your team will become the accountable owner of subsystem readiness across high-speed interface IPs, with the mandate to build an always-on, AI-enabled interoperability factory that scales across the portfolio.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":9173,"description_truncated":false,"requirements":{"experience_years_min":20,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-13T17:05:13Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":18,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-11-13T18:45:45Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-director-19735","json_url":"https://alion.io/job/synopsys-asic-digital-design-director-19735.json","meta":{"generated_at":"2026-11-13T18:45:45Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":37501,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-director-19735"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-director-19735"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-director-19735"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-director-19735\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-director-19735"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4268639}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4268639},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}