{"id":2357704,"url":"https://alion.io/job/synopsys-asic-digital-design-engineer-17918","title":"ASIC Digital Design, Engineer - 17918","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":89,"ghost_share":0.034,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":11,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Dublin, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":51000,"max_usd":126000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":621},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"HPC","optional":false},{"name":"Python","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"CI/CD","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-10-12T15:04:19Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-12T23:26:11Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence - from self-driving cars to learning machines - and we lead in chip design, verification, and IP integration that power high-performance silicon and software.\nWithin our HPC Controller IP organization, the infrastructure and release team owns the EDA tooling, automation, and quality gates that build, package, verify, and release complex soft IP at scale. We make sure every product is assembled correctly, passes its release testing, and is signed off with confidence before it reaches customers.\nYou Are:\nA motivated engineer who enjoys EDA tooling, flow automation, and owning the product release and sign-off process - with genuine enthusiasm for automation, quality, and using AI to raise engineering productivity, debug speed, and quality of results. You take ownership of getting a product packaged correctly, tested, and released on schedule. You partner naturally with design, verification, and implementation teams, communicate clearly, and let data guide your decisions. Logic-engineering know-how (synthesis, STA, and similar) is a welcome bonus rather than a prerequisite.\nWhat You’ll Be Doing:\nOwn and execute the product release process for complex soft IP: assemble and package deliverables, verify that contents and configurations are complete and correct, and produce clean release collateral.\nRun release testing and sign-off: exercise release regressions and quality gates, confirm the product is packaged correctly, and sign off deliverables before they ship to customers and downstream teams.\nDevelop, run, and maintain EDA tooling, flow automation, and project infrastructure (Tcl/Python/Make-based), plus dashboards that track release status and quality.\nDebug tooling and release failures end to end:analyzelogs and reports, isolate root cause, communicate status and risks clearly, and drive issues to closure with design, verification, and implementation teams.\nApply AI to accelerate the work (e.g., triaging flow and release logs, summarizing regression and QoRtrends, drafting and refactoring scripts).\nImprove documentation, packaging and sign-off criteria, and reusable collateral so releases stay consistent and repeatable across IP programs.\nBonus: contribute to mid-end logic flows - synthesis, DFT, static checking (SpyGlass), formal equivalence, and power analysis - where it supports release readiness.\nThe Impact You Will Have:\nProducts released on time, packaged correctly, and signed off with confidence.\nFaster, more scalable execution through stronger automation and AI-enabled analysis.\nPackaging, release, and quality-gate issues caught earlier in the cycle.\nTighter collaboration and clearer communicationacross the design-to-release chain.\nRobust, implementation-ready soft IP shipped with clear collateral, checks, and sign-off.\nWhat You’ll Need (Core):\nWorking knowledge of EDA tooling and flow/automation development, typically gained through 2+ years of relevant experience or equivalent project work.\nExperience with - or strong aptitude for - product release and sign-off: packaging deliverables, running release regressions, and verifying content and quality gates.\nGood scripting skills (Tcland/or Python) and a practical, automation-first mindset.\nComfort with build/packaging systems, revision control (e.g., Perforce or Git), and regression/CI flows.\nEnough understanding of ASIC design and verification flows to support and debug the tooling around them.\nAbility to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.\nStrong written and verbal communication skills,including the ability to summarize issues, explain release status and risks, and align cross-functional teams on next steps\nBS/MS in Electrical/Computer Engineering, Computer Science, or equivalent experience.\nNice to have (Bonus):\nHands-on logic engineering: synthesis, static timing analysis (STA), DFT, static checking (SpyGlass), formal equivalence (e.g., Formality), or power analysis.\nHands-on with Synopsys tools such as Fusion Compiler, VC SpyGlass, or Formality.\nIP development methodologies, IP packaging, or reusable IP delivery / release collateral.\nExperience building CI/CD pipelines, regression frameworks, or reporting dashboards.\nWho You Are:\nProactive, curious, and adaptable.\nCollaborative, communicative, and ethical.\nFlow-oriented, AI-aware, and quality focused.\nResilient and results oriented.\nThe Team You’ll Be APart Of:\nYou’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5414,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-12T15:04:19Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":11,"reasons":["conf:1","win:early","comp:junior,brand"],"computed_at":"2026-10-13T01:17:31Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-engineer-17918","json_url":"https://alion.io/job/synopsys-asic-digital-design-engineer-17918.json","meta":{"generated_at":"2026-10-13T01:17:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1906,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-engineer-17918"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-engineer-17918"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-engineer-17918"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-engineer-17918\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-engineer-17918"}]}