{"id":1950245,"url":"https://alion.io/job/synopsys-asic-digital-design-manager-18957","title":"ASIC Digital Design, Manager - 18957","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":63000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-06T09:38:49Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-13T17:19:13Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent a decade building IP that ships, not just passes verification. You know that the best microarchitecture is the one that survives contact with timing closure, power constraints, and the realities of a 5nm process node. You have been the person in the room who catches the CDC issue before it becomes a silicon respin, and you have learned that the hardest part of leading a design team is not writing the cleanest RTL, it is teaching five engineers to think three steps ahead without micromanaging their every line of code.\nYou are equally comfortable reviewing a timing report at 9 a.m. and having a career conversation with a junior engineer at 3 p.m. You do not just manage projects, you grow people. When someone on your team hits a wall on a complex AXI bridge implementation, you know when to step in with technical guidance and when to let them work through it. You have strong opinions about what makes good SystemVerilog and you are not afraid to push back when an architecture decision does not make sense for the product or the schedule.\nAt Synopsys, you will lead a team building Ethernet MAC and PCS controllers that power networking silicon across the industry. The work is technically hard, the team is real, and what you build will matter.\nWhat You'll Be Doing\nLead a team of digital design engineers developing Ethernet MAC and PCS IP from microarchitecture specification through customer release\nDrive architectural and microarchitectural decisions for next-generation Ethernet controllers, translating customer requirements into robust, scalable RTL implementations in SystemVerilog\nOversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across multiple concurrent IP development projects\nManage resource allocation, project execution, and cross-functional collaboration with verification, physical design, and product teams to meet schedule and quality commitments\nConduct technical interviews, assess candidate capabilities in RTL design and microarchitecture, and build a high-performing team through hiring and onboarding\nMentor engineers on complex implementation challenges including high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies\nOwn performance reviews, career development planning, and succession planning for your team while fostering a culture of technical excellence and continuous learning\nThe Impact You Will Have\nDeliver Ethernet IP that powers networking products across the semiconductor industry, enabling high-speed connectivity in data centers, automotive, and AI systems\nBuild and scale a digital design team capable of executing complex IP development projects with quality, predictability, and technical rigor\nStrengthen Synopsys IP portfolio by driving architectural innovation and design reuse across Ethernet MAC, PCS, and related high-speed interface technologies\nReduce time-to-market for customers by ensuring IP releases meet timing, power, and area targets without late-stage surprises or silicon respins\nGrow the next generation of RTL design talent through mentorship, technical coaching, and hands-on leadership in real product development\nInfluence cross-functional execution by providing clear technical direction, risk assessment, and tradeoff analysis that keeps projects on track\nShape the technical culture of the Ethernet IP group by setting standards for design quality, code reviews, and engineering discipline\nWhat You'll Need\n10+ years of hands-on ASIC digital design experience with deep expertise in RTL development, microarchitecture, and IP design\n3+ years in a technical leadership or engineering management role, with demonstrated ability to lead, mentor, and grow design teams\nExpert-level proficiency in SystemVerilog and Verilog for synthesis, with a strong track record of delivering production-quality RTL\nDeep knowledge of high-speed interfaces and protocols such as Ethernet, PCIe, DDR, or AMBA AXI/AHB/APB\nStrong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals\nHands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies\nExperience with low-power design techniques, UPF-based power intent definition, and multi-voltage domain architectures is a strong plus\nFamiliarity with advanced process nodes (7nm, 5nm, or below) or hardware/software co-verification using emulation platforms like Palladium or Zebu is a plus\nWho You Are\nYou can look at a timing report, identify the critical path, and explain to your team why the fix is not just about adding pipeline stages but rethinking the datapath architecture\nYou know the difference between mentoring someone through a tough technical problem and solving it for them, and you default to the former unless the schedule truly demands the latter\nYou ask the right questions in design reviews, the ones that uncover assumptions, expose risks, and make the team think harder about corner cases before they become bugs\nYou are comfortable having hard conversations about performance, technical gaps, or missed commitments, and you do it in a way that builds trust rather than defensiveness\nYou can explain a complex microarchitectural tradeoff to a product manager in two sentences without losing the technical nuance that matters\nYou treat hiring as seriously as you treat design reviews because you know that the quality of your team determines the quality of the IP you ship\nThe Team You'll Be Part Of\nYou will join the Synopsys Ethernet IP Group in Bengaluru, a team focused on designing and developing Ethernet MAC and PCS controllers that power networking solutions across the industry. This is a core IP design team, not an SoC integration group. The work centers on complex ASIC and IP development requiring deep RTL expertise, microarchitecture skills, and a strong understanding of high-speed interface technologies. You will collaborate closely with verification, physical design, and product teams to deliver IP that meets rigorous customer requirements for performance, power, and quality.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":7227,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":3,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-06T09:38:49Z"}],"visa":[],"liveness":{"score":74,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.826,"p_room":0.9,"age_days":6,"expected_fill_days":12,"reasons":["conf:2","velocity","win:mid","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-manager-18957","json_url":"https://alion.io/job/synopsys-asic-digital-design-manager-18957.json","meta":{"generated_at":"2026-10-13T17:48:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27206,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-manager-18957"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-manager-18957"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-manager-18957"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-manager-18957\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-manager-18957"}]}