{"id":1311335,"url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-13115","title":"ASIC Digital Design, Principal Engineer- 13115","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":75,"ghost_share":0.04,"stale_share":0,"repost_share":0.173,"time_to_fill_p50_days":15,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys ZeBu","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-22T05:08:10Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of ASIC verification, and somewhere along the way you realized that emulation is not just another tool in the flow, it is the thing that makes or breaks your ability to ship complex IP on time. You know PCIe or DDR inside and out, not just the spec but the weird corner cases, the errata that nobody talks about, and the places where emulation models fall short of what the design team actually needs.\nYou have worked on Zebu or similar platforms long enough to know what good emulation IP looks like and what happens when it is not quite right. You have closed that gap before, probably more than once, and you know how to do it without creating chaos for the teams depending on your work. You are comfortable sitting with a design team in Bangalore, a verification lead in California, and an IP product manager in Europe, and walking out with a plan that everyone believes in.\nYou do not wait for perfect alignment. You ask the right questions, you push back when something does not make sense, and you move. At Synopsys, you will work on IP that powers the next generation of silicon, and the emulation strategies you define will directly affect how fast we get there.\nWhat You'll Be Doing\nBridge the gap between Emulation IP capabilities and Design IP verification needs across both Controller and PHY domains for high speed interfaces like PCIe and DDR\nDefine technical requirements for Emulation IP, working directly with IP development and verification teams to ensure correct implementation and deployment on Zebu platforms\nTrack and report key metrics on Emulation IP quality, performance, and coverage, driving continuous improvement across verification workflows\nStay ahead of evolving PCIe and DDR standards, interpret specification updates, ECNs, and errata, and translate those into actionable changes for both Emulation and Design IP teams\nReview and validate test plans for Emulation IP and Design IP, ensuring completeness, traceability, and alignment with product quality goals\nCollaborate cross-functionally with verification, design, product, and platform teams to optimize emulation methodologies and standardize best practices\nMentor engineers on emulation strategies, verification techniques, and IP development workflows\nThe Impact You Will Have\nAccelerate time to market for high performance IP by defining emulation strategies that catch issues earlier and reduce silicon respins\nElevate product quality across Synopsys IP portfolios by ensuring Emulation IP meets the real needs of design and verification teams\nDrive adoption of best in class emulation and verification methodologies that become standard practice across the organization\nInfluence the next generation of emulation solutions and workflows, positioning Synopsys as a leader in pre-silicon validation\nImprove cross-functional collaboration and alignment between geographically distributed teams, reducing friction and rework\nStandardize verification workflows and metrics, making it easier for teams to track progress, identify gaps, and deliver with confidence\nShape how Synopsys develops and deploys Emulation IP for cutting edge digital designs and system architectures\nWhat You'll Need\n* You have 8+ years of hands-on experience in emulation, pre-silicon verification, or IP product development* You bring expert-level knowledge of PCIe or DDR interfaces, including protocol details, verification strategies, and real-world implementation challenges\n* You possess extensive experience with Zebu or similar emulation platforms, specifically for IP verification and system-level validation\n* You have a proven track record leading IP product development initiatives with a strong focus on emulation and verification\n* You have demonstrated ability to work cross-functionally in matrixed, global teams and drive consensus across diverse stakeholders\n* You possess strong communication skills with the ability to influence technical direction and inspire change across engineering teams\n* You are comfortable working in dynamic, ambiguous environments where requirements evolve and priorities shift\n\nWho You Are\nYou can walk into a room where the Emulation IP does not quite match what the design team needs and walk out with a concrete plan to close the gap without derailing either team's schedule\nYou do not need someone to tell you what the next version of the PCIe or DDR spec means for your work, you read it, figure out the implications, and start the conversation with your team\nYou are the person people come to when emulation results do not make sense, and you know how to debug across the boundary between emulation models, RTL, and test environments\nYou push back when a test plan looks complete on paper but is missing coverage for the cases that actually matter in production\nYou are comfortable mentoring engineers who are newer to emulation or IP verification, and you do it in a way that builds their confidence and capability\nYou stay organized across multiple workstreams, stakeholders, and time zones without losing track of what matters most\nThe Team You'll Be Part Of\nYou will join a dynamic, high performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation. Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry leading solutions. You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.","description_format":"text","description_chars":6651,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[],"liveness":{"score":31,"band":"fade","label":"Fading","p_open":1,"p_active":0.692,"p_room":0.45,"age_days":24,"expected_fill_days":15,"reasons":["conf:2","velocity","win:tail","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-13115","json_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-13115.json","meta":{"generated_at":"2026-10-22T05:59:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":662,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-principal-engineer-13115"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-principal-engineer-13115"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-principal-engineer-13115"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-principal-engineer-13115\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-principal-engineer-13115"}]}