{"id":1311446,"url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18713","title":"ASIC Digital Design, Principal Engineer - 18713","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":80,"ghost_share":0.038,"stale_share":0,"repost_share":0.188,"time_to_fill_p50_days":14,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Maia, Portugal"],"countries":["PT"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":58000,"max_usd":132000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:33:20Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-18T15:50:10Z","board_verified":true,"closed_at":null,"days_open":22,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":22},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade or more designing digital logic that has to hold up in real silicon, not just pass simulation, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a micro-architecture decision made six months earlier. High-speed communication protocols are your territory. You have worked on DDR, HBM, or similar interfaces enough times to know where the edge cases live and how to design around them without overbuilding.\nYou think in trade-offs. Performance, power, area, latency and timing are not separate problems to you, they are variables in the same equation, and you know how to tune them for the market you are targeting. When a circuit team hands you, specifications or timing constraints that do not quite line up, you do not escalate immediately. You ask the right questions, model the scenarios, and figure out what actually needs to change.\nMentorship matters to you. You have seen engineers grow from writing their first FSM to owning entire subsystems, and you take that progression seriously. At Synopsys, you will work on next-generation memory and compute IP for high-performance computing, and the blocks you define will ship in products that power data centers and AI infrastructure.\nWhat You'll Be Doing\nDefine micro-architecture for mixed-signal IP blocks from industry specifications and internal architecture definitions, balancing performance, power, area, latency and timing for HPC applications\nDevelop RTL for complex digital blocks within high-speed communication IP, including DDR and HBM interfaces\nModel circuit behavior for analog and mixed-signal components to enable co-design and early validation\nDefine and refine synthesis constraints, working closely with physical design and timing closure teams to ensure your blocks meet targets\nRun and review code quality checks (Lint, CDC and RDC analysis), catching issues early in the development cycle\nEvaluate design trade-offs across multiple dimensions and recommend solutions that align with product goals and market requirements\nMentor engineers on your team, reviewing designs, providing technical guidance, and helping them build the judgment that comes with experience\nThis position could be performance in Lisbon and Porto.\nThe Impact You Will Have\nYour micro-architecture decisions will define the performance and efficiency profile of next-generation memory IP used in high-performance computing systems\nThe RTL you develop will be synthesized, verified, and manufactured in leading-edge process nodes, directly affecting product competitiveness\nYour behavioral models will enable early co-design between digital and analog teams, reducing integration risk and schedule slip\nThe constraints and design practices you establish will set the quality bar for the broader IP development team\nYour mentorship will accelerate the growth of engineers around you, building the technical depth the team needs to scale\nThe trade-off analysis you provide will inform product roadmap decisions and help leadership prioritize the right features for the right markets\nYour attention to CDC, RDC, and code quality will reduce downstream debug time and improve first-pass silicon success rates\nWhat You'll Need\nMaster's degree in Electrical Engineering, Computer Engineering, or a related field\n10+ years of hands-on ASIC digital design experience, with a strong track record of blocks that have taped out and worked\nDeep expertise in high-speed communication protocols, specifically DDR, HBM, or similar memory interfaces\nSolid understanding of low power design techniques and how to apply them in performance-critical contexts\nStrong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) analysis, and experience resolving violations in complex designs\nExperience with synthesis flows, including physical-aware synthesis and constraint definition for timing closure\nFamiliarity with mixed-signal design environments and the ability to work effectively with circuit designers and behavioral models is a strong plus\nWho You Are\nYou can walk into a room with architects, analog designers, and verification engineers, listen to three conflicting constraints, and walk out with a design approach that actually works for all of them\nWhen you review RTL, you do not just check for syntax. You are looking at the structure, the reusability, the assumptions baked into the logic, and whether it will hold up under corner cases\nYou are process-oriented in the best sense. When something breaks, you want to know why it broke and what upstream decision allowed it to happen, not just how to patch it\nDetail matters to you. You catch the subtle bugs, the edge cases in the spec, the constraint that is slightly off, because you know those are the things that cost weeks in the lab later\nYou are comfortable navigating a multi-team environment where your block touches verification, physical design, circuit design, and system architecture, and you know how to keep all those threads aligned without losing momentum\nYou take mentorship seriously. You make time to review a junior engineer's design, explain why a different approach might scale better, and help them build the instincts that only come from doing the work\nThe Team You'll Be Part Of\nYou will be part of a multi-discipline product development team working on next-generation IP for high-performance computing. The work spans digital design, mixed-signal integration, verification, and physical implementation, and you will collaborate across all of those functions. The team is solving complex engineering challenges at the intersection of performance, power, and manufacturability, and the products you help build will be used in data centers and AI systems worldwide.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6744,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:33:20Z"},{"event":"close","at":"2026-10-13T09:21:34Z"},{"event":"reopen","at":"2026-10-13T17:19:13Z"}],"visa":[],"liveness":{"score":37,"band":"fade","label":"Fading","p_open":1,"p_active":0.666,"p_room":0.55,"age_days":20,"expected_fill_days":14,"reasons":["conf:0","velocity","win:tail","comp:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18713","json_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18713.json","meta":{"generated_at":"2026-10-18T17:04:40Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22402,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18713"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18713"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18713"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-principal-engineer-18713\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18713"}]}