{"id":2667906,"url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18730","title":"ASIC Digital Design, Principal Engineer - 18730","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":["CA"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":86000,"max_usd":148000,"period":"year","method":"role_seniority_country_cell","sample_n":16},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-10-16T03:19:36Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-20T04:31:56Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Description and Requirements\nNote: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade or more designing digital logic that has to work at the edge of what silicon can do. High-speed SerDes, clock domain crossings that could sink a tapeout, power budgets measured in milliwatts because every one counts. You know that the hardest part of mixed-signal ASIC design is not the RTL, it is the boundary between digital and analog, where timing meets noise and specifications meet reality. You have debugged gate-level sims at 2 a.m. and found the one async crossing that everyone else missed.\nYou think in terms of design intent, not just passing checks. When you write Verilog, you are already thinking about what synthesis will do to it, what DFT will need, and how verification will cover it. You do not hand off a block and hope for the best. You sit with the verification team, you walk through the testplan, and you help debug the failures that matter.\nMentorship is not a checkbox for you. You have brought junior engineers along, shown them how to think through a problem instead of just fixing their code. At Synopsys, you will architect digital logic for next-generation Ethernet, PCIe, SATA, and USB PHYs that ship in products around the world. The team is expert-level, the problems are real, and what you design will matter.\nWhat You'll Be Doing\nArchitect and design digital subsystems for high-speed SerDes IP including Backplane Ethernet, PCIe, SATA, and USB 2/3 PHYs\nAnalyze and define digital and analog interface specifications, translating system-level requirements into implementable RTL and design constraints\nDrive design flow decisions for clock domain crossing, synthesis, DFT insertion, and low-power architecture across complex mixed-signal blocks\nCollaborate directly with ASIC verification engineers to define testplans, review assertion and code coverage, and close functional coverage gaps\nPerform gate-level simulation, analyze timing and power, and debug failure cases across digital and mixed-signal boundaries\nMentor junior design engineers on RTL quality, design intent, synthesis impact, and cross-functional collaboration\nWork across design groups and customer support teams to resolve design issues, clarify specifications, and support silicon bring-up\nThe Impact You Will Have\nYour architectural decisions will define the performance, power, and area of SerDes IP used in high-volume networking and storage products worldwide\nThe design flows and methodologies you establish will set the standard for how the team handles CDC, DFT, and low-power design across future product generations\nYour collaboration with verification will reduce tapeout risk and catch critical issues before they reach silicon\nThe testplans and coverage strategies you help create will directly improve functional quality and reduce post-silicon debug cycles\nYour mentorship will accelerate the growth of junior engineers and raise the technical bar across the team\nThe specifications you write will become the foundation for cross-functional alignment between digital, analog, verification, and implementation teams\nYour work will enable customers to deliver faster, lower-power, more reliable connectivity in everything from data centers to consumer devices\nWhat You'll Need\nMaster's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience\n10+ years of hands-on digital ASIC design experience, with significant work in high-speed or mixed-signal environments\nStrong proficiency in Verilog or VHDL for RTL design and gate-level simulation\nDeep understanding of clock domain crossing design, analysis, and verification methodologies\nHands-on experience with synthesis tools and techniques, including timing closure and power optimization\nSolid knowledge of DFT methodologies including scan insertion, ATPG, and boundary scan\nExperience working closely with verification teams on testplan creation, coverage closure, and failure analysis. Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB is a strong plus.\nWho You Are\nYou can look at a block diagram and immediately spot the async crossing that is going to cause problems three months from now\nYou write RTL with synthesis in mind, not as an afterthought, and you know how to balance design intent with tool limitations\nYou are comfortable sitting with an analog designer to hash out an interface spec, then turning around and explaining the same thing to a verification engineer in a way that makes sense for testbench architecture\nYou do not wait for perfect documentation. You ask the right questions, fill in the gaps, and move forward without creating downstream confusion\nYou have strong opinions about code quality, coverage metrics, and design methodology, and you are willing to push back when something does not make sense\nYou can explain a complex timing or power tradeoff to a senior leader in two sentences without losing the technical nuance\nThe Team You'll Be Part Of\nYou will join a highly experienced mixed-signal design team responsible for delivering industry-leading SerDes IP for Backplane Ethernet, PCIe, SATA, and USB standards. This team works across the full design cycle, from early specification development through silicon validation and customer support. Your recruiter will share more about the team structure, current product roadmap, and collaboration model during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":6691,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-16T03:19:36Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":14,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18730","json_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18730.json","meta":{"generated_at":"2026-10-20T04:43:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5318,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18730"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18730"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18730"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-principal-engineer-18730\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18730"}]}