{"id":2688581,"url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18914","title":"ASIC Digital Design, Principal Engineer - 18914","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence AMS Designer","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-16T08:19:09Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-23T23:40:59Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years at the intersection of digital and analog verification, and you know that the hardest part of any SerDes project is not just proving the logic works, but proving it works when the analog world throws noise, jitter, and timing chaos at it. You think in test plans, not test cases. You understand that a good verification strategy catches the corner case at block level, not during customer bring-up six months later.\nLeading a team is not new to you. You have been the person who turns a group of talented engineers into a unit that ships on time without cutting corners. You know when to dive into a waveform yourself and when to step back and let your team own the debug. You have debugged enough mixed-signal simulations to know that the answer is usually hiding in the handoff between domains, and you are comfortable living in that space.\nHigh-speed interfaces like PCIe, Ethernet, and USB3.1 are not buzzwords to you, they are protocols you have verified, debugged, and shipped. You ask the right questions during architecture reviews because you have seen what happens when assumptions go unchecked. At Synopsys, you will lead verification for SerDes IP that powers the chips inside everything from data centers to autonomous vehicles.\nWhat You'll Be Doing\nLead a verification team working on current and next-generation SerDes products, setting direction, reviewing test plans, and ensuring coverage closure across digital and mixed-signal domains\nModify and extend existing UVM and VMM SystemVerilog testbenches to co-simulate mixed-signal designs, bridging digital logic with analog models in tools like AMS Designer or Xcelium\nAnalyze and verify high-speed SerDes functionality including clock data recovery, equalization, and link training across protocols like PCIe Gen5/6, 400G Ethernet, and USB3.1\nDefine verification test plans with clear coverage goals, track progress against milestones, and drive closure on functional, code, and assertion coverage\nDebug simulation failures that span both analog waveforms and digital logic, working with mixed-signal engineers to isolate root cause and validate fixes\nManage customer escalations on verification quality, silicon bugs, or testbench issues, and lead pre-sales technical discussions to support customer evaluations and design wins\nThe Impact You Will Have\nEnsure SerDes IP used in data centers, automotive, and AI infrastructure ships with the quality and performance customers depend on\nDrive verification methodology improvements that reduce simulation time, increase coverage efficiency, and catch bugs earlier in the design cycle\nBuild and mentor a verification team that delivers consistently, owns their work, and raises the bar on quality with every tapeout\nShape the verification strategy for next-generation SerDes products, influencing architecture decisions before RTL is written\nReduce customer-found issues by tightening verification rigor and improving handoff quality between digital, analog, and system teams\nContribute to Synopsys IP leadership by ensuring our SerDes portfolio remains best-in-class for performance, reliability, and time-to-market\nWhat You'll Need\nMTech or BTech with 15+ years of hands-on verification experience in ASIC development, with significant time spent on mixed-signal or SerDes designs\nDeep knowledge of the full ASIC development flow from architecture specification through digital design, verification, physical implementation, and hardware bring-up\nExtensive experience building and running UVM testbenches, including writing constrained random tests, developing scoreboards, and managing coverage-driven verification closure\nPractical experience with digital/analog co-simulation methodologies using tools like Cadence AMS Designer, Synopsys VCS AMS, or equivalent mixed-signal simulation environments\nStrong understanding of high-speed interface protocols such as PCIe (Gen3 or higher), Ethernet (10G/25G/50G/100G/400G), USB3.1, or similar SerDes-based standards\nProven ability to lead technical teams, manage customer escalations, and communicate complex verification issues clearly to both engineering teams and external stakeholders\nExperience debugging at the boundary between digital logic and analog circuits, including familiarity with reading SPICE netlists, interpreting analog waveforms, and understanding signal integrity concepts is a strong plus\nWho You Are\nYou can walk into a design review, ask three questions, and identify the verification risk everyone else missed because you have seen that failure mode before\nYou lead by example, you will debug a tough simulation failure alongside your team at 9pm if that is what it takes, but you also know when to delegate and trust your engineers to own the solution\nYou are comfortable telling a senior architect that their assumption needs a directed test because you have learned that undocumented corner cases become customer bugs\nYou manage multiple priorities without losing track of details, you know which bug needs to be fixed today and which one can wait until after the next milestone\nYou communicate trade-offs clearly, whether you are explaining coverage gaps to your manager or walking a customer through a testbench limitation in a pre-sales call\nYou build teams that stay, people work for you because you make them better engineers, not because you micromanage their every move\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6572,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-16T08:19:09Z"}],"visa":[],"liveness":{"score":77,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.856,"p_room":0.9,"age_days":6,"expected_fill_days":15,"reasons":["conf:1","velocity","win:mid","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18914","json_url":"https://alion.io/job/synopsys-asic-digital-design-principal-engineer-18914.json","meta":{"generated_at":"2026-10-23T23:49:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7486,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18914"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18914"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18914"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-principal-engineer-18914\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-principal-engineer-18914"}]}