ASIC Digital Design, Sr Engineer

Job Description and Requirements

You Are

You are an ASIC digital designer who has taken RTL modules from specification through implementation and into production silicon. You write timing-aware Verilog, and you use synthesis, timing, and power results to improve your designs. You work closely with architecture, verification, and physical design, and you raise tradeoffs early so performance, area, and power stay aligned with the schedule. When specifications change, you analyze the impact and propose a practical path forward. At Synopsys, you will design modules in the UCIe Controller IP used in high-performance computing applications.

What You'll Be Doing

• Design and own RTL modules for UCIe Controller IP, from microarchitecture through synthesis-ready implementation, with guidance from senior designers
• Tune your modules to meet timing, power, and area targets, and incorporate feedback from synthesis and timing analysis across process nodes
• Develop Python, Tcl, and Perl scripts for design generation and flow integration
• Participate in design reviews and contribute improvements to team methodology

The Impact You Will Have

• Your modules will ship in UCIe IP used in high-volume HPC, automotive, and AI products
• You will help deliver a core Synopsys product line while building depth in controller and high-speed interface design

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 2-3 years of ASIC digital design experience, including ownership of RTL modules in production or near-production silicon
• Strong Verilog skills for timing-critical designs
• Working proficiency in Python, Tcl, or Perl for design automation
• Hands-on experience with synthesis, static timing analysis, and power optimization
• Experience with controller IP or high-speed interfaces is preferred

Who You Are

• You connect RTL structure to timing and power results and adjust the design accordingly
• You communicate clearly with architects, verification engineers, and physical designers
• You write readable, maintainable code that other engineers can review and extend
• You suggest practical improvements to design and automation flows
• You debug issues methodically and follow them through to a verified fix

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.