{"id":1311355,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-18436","title":"ASIC Digital Design, Sr Engineer - 18436","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":90,"ghost_share":0.033,"stale_share":0,"repost_share":0.144,"time_to_fill_p50_days":10,"computed_at":"2026-10-03T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hanoi, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":44000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1198},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-03T22:07:45Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nAlternate Job Titles\nDesign Verification Engineer\nDigital Verification Engineer\nRTL Verification Engineer\nIP Verification Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years proving that silicon actually worksthe way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeoutinto a respin, and building the infrastructure to catch those problems before they become expensive.\nYou are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually firewhen something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.\nMixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.\nAt Synopsys, you will work on IP that powers the chips inside the deviceschanging how the world connects, computes, and moves.\nWhat You'll Be Doing\nDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure\nWrite test cases, assertions, and checkers in SystemVerilogto ensure comprehensive functional coverage\nDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi\nDrive coverage analysis and closure across code, functional, and assertion metrics\nParticipate in technical and peer reviews to ensure verification quality and process adherence\nCollaborate with design, architecture, and silicon validation teams to identify and resolve issues early\nThe Impact You Will Have\nEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applications\nReduce costly respinsand post-silicon debug cycles by catching critical bugs early through rigorous verification\nContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliability\nEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IP\nStrengthen verification methodologies that scale across global engineering teams\nMentor and elevate the skills of the Vietnam engineering team through knowledge sharing\nWhat You'll Need\nBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field\n2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP\nStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies\nExperience with VCS and Verdi for simulation and debug\nSolid understanding of verification planning, coverage-driven verification, and assertion-based verification\nFamiliarity with formal verification tools like vc_formalis a plus\nScripting experience in Perl, TCL, or Python is a plus\nWho You Are\nYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptom\nYou can explain a complex verification failure to a design engineer in a way that gets them to the fix faster\nYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestone\nYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being asked\nYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan\nThe Team You'll Be Part Of\nYou will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5674,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[],"liveness":{"score":71,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.789,"p_room":0.9,"age_days":6,"expected_fill_days":10,"reasons":["conf:29","velocity","win:mid","comp:brand"],"computed_at":"2026-10-03T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-18436","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-18436.json","meta":{"generated_at":"2026-10-04T00:28:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":562,"day_limit":5000,"remaining_today":4438,"minute_limit":60,"resets_at":"2026-10-05T00:00:00Z"}}}