{"id":4268640,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-19577","title":"ASIC Digital Design, Sr Engineer - 19577","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true}],"status":"live","first_seen_at":"2026-11-13T17:05:13Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T17:05:13Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent the last few years building verification environments that actually catch bugs before tapeout, and you know the difference between a testbench that looks complete and one that actually stresses the design. UVM is not just a framework you have heard about, it is something you have used to build real testbenches, debug real failures, and close coverage gaps that mattered.\nYou are comfortable reading a specification, asking the questions that are not written down, and turning that into a verification plan that makes sense. When a simulation fails at 3pm, you do not wait for someone to tell you what to do. You dig into waveforms, trace the issue, and figure out whether it is a test problem, an environment problem, or an actual design bug.\nProtocols are not intimidating to you. Maybe you have worked with one already, maybe you have not, but you know how to read a spec, understand timing diagrams, and build checkers that enforce the rules. You are the kind of engineer who wants to get better, who asks good questions, and who does not need to be the smartest person in the room to contribute something real.\nAt Synopsys, you will work with people who have been doing this for years and who will help you grow.\nWhat You'll Be Doing\nAnalyze design specifications and identify what needs to be verified, including functionality, interfaces, edge cases, and protocol compliance\nBuild and extend UVM-based verification environments in System Verilog, working alongside a technical lead to define architecture and reusable components\nWrite directed and constrained-random tests, implement functional checkers, and develop coverage models to track verification progress\nDebug simulation failures by analyzing waveforms, logs, and coverage reports to isolate root causes in the testbench or design\nCollaborate with design engineers to understand RTL changes and with the VIP team to integrate and leverage verification IP effectively\nContribute to test planning, code reviews, and process improvements that help the team close verification faster and with higher quality\nFollow established verification methodologies and quality standards while identifying opportunities to improve flow efficiency\nThe Impact You Will Have\nYour verification environments will catch critical design issues before they reach silicon, saving months of debug time and reducing tapeout risk\nThe test scenarios and checkers you build will directly improve functional coverage closure and give the team confidence in design correctness\nYour collaboration with design engineers will surface ambiguities and corner cases early, leading to cleaner RTL and fewer late-stage surprises\nThe verification IP and reusable components you help develop will be leveraged across multiple projects, accelerating future verification efforts\nYour contributions to test planning and coverage analysis will help the team make data-driven decisions about when a block is ready to integrate\nThe questions you ask and the gaps you identify will strengthen specifications and improve the overall quality of the product\nYour willingness to learn new protocols and methodologies will expand the team's capability and enable support for more complex designs\nWhat You'll Need\nBachelor's degree in Electronics Engineering, Electrical Engineering, or a closely related field\nAt least 3 years of hands-on experience in digital design verification\nProficiency in Verilog and System Verilog, with a working understanding of UVM methodology and testbench architecture\nExperience writing and debugging testbenches, including constrained-random testing, functional coverage, and assertion-based verification\nAbility to read and interpret design specifications, timing diagrams, and interface protocols\nExperience with a standard protocol such as AXI, PCIe, USB, or Ethernet is a plus\nFamiliarity with simulation tools like VCS, Questa, or Xcelium is a plus\nWho You Are\nYou can take a 50-page specification, pull out what matters for verification, and turn it into a test plan without needing someone to walk you through every line\nWhen a test fails, you do not stop at \"it is broken,\" you trace it back to the root cause and explain what went wrong in a way that helps the designer fix it quickly\nYou manage your own work without needing daily direction, you know what is blocking you, what is next, and when to ask for help\nYou communicate clearly in English, both in writing and in conversation, whether you are documenting a coverage gap or explaining a simulation failure in a team meeting\nYou are comfortable working with people across functions, design engineers who need clear bug reports, VIP teams who need integration feedback, and leads who need status without fluff\nLearning a new protocol or verification technique does not intimidate you, it is just part of the job, and you are willing to put in the work to get up to speed\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5952,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-13T17:05:13Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":18,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-11-13T18:10:31Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-19577","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer-19577.json","meta":{"generated_at":"2026-11-13T18:10:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":36372,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-engineer-19577"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"free","price":{"credits":0,"usd":0},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-engineer-19577"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-engineer-19577"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-engineer-19577\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-engineer-19577"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4268640}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4268640},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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