{"id":2933430,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer","title":"ASIC Digital Design, Sr Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-20T15:21:18Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-20T23:16:56Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nYou Are\nYou are an ASIC digital designer who has taken RTL modules from specification through implementation and into production silicon. You write timing-aware Verilog, and you use synthesis, timing, and power results to improve your designs. You work closely with architecture, verification, and physical design, and you raise tradeoffs early so performance, area, and power stay aligned with the schedule. When specifications change, you analyze the impact and propose a practical path forward. At Synopsys, you will design modules in the UCIe Controller IP used in high-performance computing applications.\nWhat You'll Be Doing\nDesign and own RTL modules for UCIe Controller IP, from microarchitecture through synthesis-ready implementation, with guidance from senior designers\nTune your modules to meet timing, power, and area targets, and incorporate feedback from synthesis and timing analysis across process nodes\nDevelop Python, Tcl, and Perl scripts for design generation and flow integration\nParticipate in design reviews and contribute improvements to team methodology\nThe Impact You Will Have\nYour modules will ship in UCIe IP used in high-volume HPC, automotive, and AI products\nYou will help deliver a core Synopsys product line while building depth in controller and high-speed interface design\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field\n2-3 years of ASIC digital design experience, including ownership of RTL modules in production or near-production silicon\nStrong Verilog skills for timing-critical designs\nWorking proficiency in Python, Tcl, or Perl for design automation\nHands-on experience with synthesis, static timing analysis, and power optimization\nExperience with controller IP or high-speed interfaces is preferred\nWho You Are\nYou connect RTL structure to timing and power results and adjust the design accordingly\nYou communicate clearly with architects, verification engineers, and physical designers\nYou write readable, maintainable code that other engineers can review and extend\nYou suggest practical improvements to design and automation flows\nYou debug issues methodically and follow them through to a verified fix\n At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":2542,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-20T15:21:18Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":14,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-10-20T23:35:52Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-engineer.json","meta":{"generated_at":"2026-10-20T23:35:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27206,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-engineer"}]}