{"id":1937384,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-18730","title":"ASIC Digital Design, Sr Manager-18730","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mississauga, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":67000,"max_usd":121000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":64},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-06T00:11:10Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-20T08:57:20Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams-architecture, verification, physical implementation, and firmware-to deliver industry-leading SERDES PHY IP solutions.\nYour leadership style is empowering, fostering growth and development within your team, and you’re committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and powers target while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you’re excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you.\nWhat You’ll Be Doing:\nLeading a diverse team of design engineering the development of next-generation SERDES PHY IP solutions.\nCollaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.\nPlanning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.\nEnsuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.\nMentoring and developing team members, fostering technical growth, and a culture of innovation.\nEngaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.\nThe Impact You Will Have:\nDelivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency.\nEmpowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.\nDriving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.\nMentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.\nEnhancing product quality and reliability through rigorous design and verification processes/Flows.\nFacilitating successful customer adoption and satisfaction through expert support and problem-solving.\nWhat You’ll Need:\nBachelor’s degree or higher in Electrical Engineering, with 15 +years of complex technical development experience.\nMinimum 2 years’ experience in people management and employee development.\nProficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation.\nStrong background in front-end design flows: Linting, synthesis, static timing analysis (STA),CDC/RDC, DFT, and power optimization.\nExcellent communication skills and the ability to work independently and collaboratively.\nUnderstanding the PCIe and Ethernet standard is a plus.\nWho You Are:\nSelf-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure.\nStrong problem-solver with a strategic, analytical mindset.\nInspirational leader who motivates and develops technical talent.\nCollaborative team players who excels in cross-functional environments.\nEffective communicator who can translate complex technical concepts to diverse audiences.\nThe Team You’ll Be A Part Of:\nYou’ll join the Synopsys SERDES PHY IP team-a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #LI-NK4\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":5248,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-06T00:11:10Z"}],"visa":[],"liveness":{"score":43,"band":"fade","label":"Fading","p_open":1,"p_active":0.778,"p_room":0.55,"age_days":14,"expected_fill_days":14,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-18730","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-18730.json","meta":{"generated_at":"2026-10-20T09:34:19Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10437,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-manager-18730"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-manager-18730"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-manager-18730"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-manager-18730\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-manager-18730"}]}