ASIC Digital Design, Sr Manager-18780

Job Description and Requirements

You Are:

You are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/System Verilog and are experienced in developing and managing testbenches in UVM environments. You are a natural leader with a proven track record of guiding and motivating teams to achieve their goals. Your expertise in memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools positions you as an invaluable asset to any team. Your problem-solving skills, coupled with your ability to communicate effectively, enable you to navigate complex technical challenges and deliver high-quality solutions. You thrive in dynamic, multi-site environments and are driven by a passion for continuous learning and growth.

What You’ll Be Doing:

Specify, design/architect, and implement IP Design and/or Verification environments for synthesizable DesignWare cores.

Lead a team, guiding them towards the closure of day-to-day design and/or verification activities.

Work closely with RTL designers, Architects, and Verification Engineers as part of a global team.

Understand design specifications and develop RTL code, test plans, and testbenches at both unit and system levels.

Ensure product release milestones are met through effective regression debug triaging and verification activities.

Contribute to the development and implementation of NextGen DesignWare HBM IPs, fostering a culture of continuous improvement and innovation.

The Impact You Will Have:

Drive the successful design and verification of high-performance memory controller IPs, contributing to the advancement of cutting-edge technology.

Ensure the timely and high-quality release of IP products that meet stringent industry standards.

Enhance the efficiency and effectiveness of design and verification processes through leadership and technical expertise.

Foster a collaborative and innovative team environment, enabling the professional growth and development of team members.

Support the strategic goals of Synopsys by contributing to the development of industry-leading IP solutions.

Strengthen Synopsys' reputation as a leader in the semiconductor industry through the delivery of high-quality, reliable products.

What You’ll Need:

BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.

Experience in leading a team of engineers and guiding them towards achieving project milestones.

Hands-on experience in RTL design and/or verification of complex designs at the IP or SoC level.

Strong knowledge of Verilog/System Verilog and experience in developing testbenches in UVM environments.

Experience with memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools.

Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills.

Who You Are:

A strong team leader and motivator with a go-getter attitude.

A technical contributor with expertise in System Verilog/Verilog RTL coding and testbench development.

Capable of creating deliverables that meet high standards without requiring close supervision.

Skilled in understanding design and verification milestones and aligning team tasks accordingly.

Experienced in improving coverage metrics and defining additional test cases.

Familiar with HDLs such as Verilog and scripting languages like shell/Perl/Python.

A good team player with strong interpersonal and communication skills.

Highly motivated and self-propelled, thriving in a project and team-oriented environment.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.