{"id":2107643,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-19159","title":"ASIC Digital Design, Sr Manager - 19159","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mississauga, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":66000,"max_usd":118000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":64},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-08T20:57:42Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-20T12:46:01Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":11},"description":"Job Description and Requirements\nYou Are:\nYou are a seasoned professional with a robust background in the design and verification of IP cores and/or SOC. You have a strong command of Verilog/SystemVerilog and are experienced in developing and managing testbenches in UVM environments. You are a natural leader with a proven track record of guiding and motivating teams to achieve their goals. Your expertise in high-speed interface protocols like PCIe/Ethernet and familiarity with IP design and verification tools positions you as an invaluable asset to any team. Your problem-solving skills, coupled with your ability to communicate effectively, enable you to navigate complex technical challenges and deliver high-quality solutions. You thrive in dynamic, multi-site environments and are driven by a passion for continuous learning and growth.\nWhat You’ll Be Doing:\nSpecify, design, architect, and implement Digital Verification environments for our next-generation SERDES PHY IP solutions.\nLead a team, guiding them towards the closure of day-to-day verification activities.\nWork closely with RTL designers, Architects, and Verification Engineers as part of a global team.\nUnderstand design specifications and develop test plans and testbenches at both unit and system levels.\nEnsure product release milestones are met through effective regression debug triaging and verification activities.\nContribute to the development and implementation of our next-generation SERDES PHY IP solutions, fostering a culture of continuous improvement and innovation.\nThe Impact You Will Have:\nDrive the successful design and verification of high-performance memory controller IPs, contributing to the advancement of cutting-edge technology.\nEnsure the timely and high-quality release of IP products that meet stringent industry standards.\nEnhance the efficiency and effectiveness of design and verification processes through leadership and technical expertise.\nFoster a collaborative and innovative team environment, enabling the professional growth and development of team members.\nSupport the strategic goals of Synopsys by contributing to the development of industry-leading IP solutions.\nStrengthen Synopsys' reputation as a leader in the semiconductor industry through the delivery of high-quality, reliable products.\nWhat You’ll Need:\nBS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.\nExperience in leading a team of engineers and guiding them towards achieving project milestones.\nHands-on experience in verification of complex designs at the IP or SoC level.\nStrong knowledge of Verilog/SystemVerilog and experience in developing testbenches in UVM environments.\nProficiency in Perl/Python-based automation and excellent communication and problem-solving skills.\nUnderstanding the PCIe and Ethernet standards is a plus.\nWho You Are:\nA strong team leader and motivator with a go-getter attitude.\nA technical contributor with expertise in SystemVerilog testbench development.\nCapable of creating deliverables that meet high standards without requiring close supervision.\nSkilled in understanding design and verification milestones and aligning team tasks accordingly.\nExperienced in improving coverage metrics and defining additional test cases.\nFamiliar with HDLs such as Verilog and scripting languages like shell/Perl/Python.\nA good team player with strong interpersonal and communication skills.\nHighly motivated and self-propelled, thriving in a project and team-oriented environment.\nThe Team You’ll Be A Part Of:\nYou’ll join the Synopsys SERDES PHY IP team-a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":4619,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-08T20:57:42Z"}],"visa":[],"liveness":{"score":62,"band":"ok","label":"Likely open","p_open":1,"p_active":0.824,"p_room":0.75,"age_days":11,"expected_fill_days":14,"reasons":["conf:1","velocity","win:late","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-19159","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-manager-19159.json","meta":{"generated_at":"2026-10-20T15:05:18Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16995,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-manager-19159"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-manager-19159"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-manager-19159"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-manager-19159\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-manager-19159"}]}