{"id":1311443,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-17919","title":"ASIC Digital Design, Sr Staff Engineer 17919","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":76,"ghost_share":0.039,"stale_share":0,"repost_share":0.171,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Dublin, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":104000,"max_usd":215000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"FMEA","optional":false},{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:33:20Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-22T05:08:10Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building digital IP that has to meet ISO 26262 ASIL D, not just pass functional verification. You know the difference between a controller that works in simulation and one that survives FMEDA, DFMEA, and real-world automotive stress, and you have debugged enough corner cases to know where those gaps usually hide. You think in RTL, but you also think in safety mechanisms, fault injections, and what it takes to qualify hardware for a car that cannot fail.\nYou are comfortable leading RTL development for a PCIe or DDR controller while also mentoring engineers through lint cleanup, CDC convergence, and synthesis QoR.\nWhat You'll Be Doing\nDesign and own RTL for automotive digital IP blocks, with a focus on PCIe, DDR, or UCIe controllers that meet ISO 26262 functional safety requirements\nLead RTL coding, lint and CDC analysis, synthesis optimization, and debug across complex IP subsystems\nWork closely with verification teams to define Verification IP scope, identify feature coverage gaps, and ensure controllers are fully validated before tapeout\nDrive safety qualification activities including DFMEA, FMEDA, and DFA for IP targeting ASIL D\nMentor and guide engineering teams through design flows, coding standards, and best practices for synthesizable Verilog and System Verilog\nApply and evaluate AI-driven design tools and methodologies to improve design quality and automation\nThe Impact You Will Have\nEnable Synopsys automotive IP to meet the most stringent functional safety standards, supporting customers building ASIL D systems\nDeliver production-quality RTL for high-speed interface IP that powers next-generation automotive SoCs\nReduce design cycle time and improve quality by introducing AI-driven design flows and automation\nClose critical gaps between design intent and verification coverage, preventing late-stage bugs and costly respins\nWhat You'll Need\nBachelor's degree with 8+ years or Master's degree with 6+ years of relevant experience in Automotive SoCs or Digital IPs\nProven IP-level experience with protocols like PCIe, DDR, or UCIe, with PCIe experience strongly preferred\nDemonstrated ability to work as an individual contributor while mentoring and leading engineering teams through RTL coding, lint/CDC analysis, synthesis, and debug\nExperience qualifying embedded hardware systems to ISO 26262 ASIL levels up to ASIL D, and working with DFMEA, FMEDA, and DFA\nIn-depth experience writing synthesizable Verilog/System Verilog for ASIC design and simulation tools\nStrong command of ASIC design flows, including lint, CDC, synthesis, Static Timing Analysis, and formal verification\nWho You Are\nYou can explain a complex safety tradeoff to a systems architect in two sentences without losing the technical nuance\nYou push back when a verification plan misses a critical fault scenario or a design spec leaves ambiguity that will cost time later\nYou are organized enough to manage RTL delivery, safety documentation, and team mentorship in parallel without dropping threads\nYou treat design automation as part of the job, not an afterthought, and you write scripts that others on the team actually use\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":4334,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:33:20Z"}],"visa":[],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.738,"p_room":0.45,"age_days":25,"expected_fill_days":15,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-17919","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-17919.json","meta":{"generated_at":"2026-10-22T06:46:32Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1898,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-17919"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-17919"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-17919"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-17919\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-17919"}]}