{"id":1311234,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18308","title":"ASIC Digital Design, Sr Staff Engineer - 18308","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-20T08:57:20Z","board_verified":true,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years verifying complex IP and you know the difference between a verification plan that looks complete on paper and one that actually catches the corner case that would have escaped to silicon. Ownership is not a buzzword for you, it is how you work. When you take on an IP or subsystem, you see the entire arc from architecture through signoff, and you know which risks matter in week two versus week twenty.\nYou do not wait for someone to tell you the methodology is broken. You see it, you fix it, and you bring the rest of the team along. Leading without a title comes naturally because people trust your judgment and your ability to translate a messy verification problem into a plan that actually closes coverage. You have debugged enough failing tests to know when to dig deeper and when to step back and rethink the approach.\nMentorship matters to you, not as a checkbox but because you remember the engineer who showed you how to think about verification strategy, and you want to be that person for someone else. At Synopsys, you will work on DesignWare IP that powers the next generation of silicon, and the verification quality you drive will be the difference between a product that ships and one that does not.\nWhat You'll Be Doing\nOwn verification for a major IP block, subsystem, or cross-IP methodology from architecture definition through final signoff and customer delivery\nDefine verification strategy, planning, architecture, and signoff criteria for complex IP projects including Ethernet, USB, and similar industry-standard protocols\nLead technical execution across verification teams by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure\nApply AI-assisted verification techniques to intelligent debug, regression analytics, test generation, and coverage closure to measurably reduce cycle time and improve defect detection\nBuild and drive reusable verification infrastructure, UVM environments, and methodology improvements that scale across multiple IP domains and projects\nMentor verification engineers on test planning, debug strategies, coverage analysis, and verification best practices while fostering technical growth across the team\nCollaborate with design, architecture, firmware, and quality teams to align verification deliverables with project goals and ensure high-quality IP releases\nThe Impact You Will Have\nDeliver thoroughly verified, customer-ready DesignWare IP that reduces integration risk and increases confidence for silicon teams building next-generation products\nDrive measurable improvements in verification efficiency including faster coverage closure, shorter regression cycles, reduced debug time, and fewer escaped defects\nAdvance verification methodologies and reusable infrastructure that improve execution quality and delivery predictability across IP projects\nStrengthen the technical capability of the verification organization by mentoring engineers and establishing best practices that scale\nReduce project risk by identifying verification gaps early, optimizing processes, and ensuring robust signoff criteria are met before release\nEnable Synopsys to maintain leadership in IP quality and reliability during the era of pervasive intelligence and AI-powered silicon design\nContribute to the success of customers who depend on Synopsys IP to power critical functions in their chips, from data centers to automotive to mobile devices\nWhat You'll Need\nBS or BE in Electrical or Electronics Engineering with 8+ years of IP or SoC verification experience, or MS with 6+ years\nDemonstrated ownership of verification for complex IP blocks, subsystems, or cross-project methodologies with a track record of delivering measurable quality and coverage results\nProven ability to lead verification teams and projects through technical influence, expertise, and collaboration rather than formal management authority\nDeep hands-on expertise in UVM, VMM, or OVM methodologies applied to real verification environments at unit and system levels\nStrong proficiency in SystemVerilog, industry-standard simulators like VCS, and associated debug tools used in complex IP verification workflows\nPractical experience applying AI-assisted methods to debug, regression optimization, test generation, or verification closure activities\nExperience with DesignWare IP or similar synthesizable IP verification, and familiarity with protocols such as Ethernet, USB, or PCI Express is a strong plus\nWho You Are\nYou lead through expertise and influence, not authority, and engineers follow your technical direction because they trust your judgment and your ability to solve hard problems\nYou own complex verification areas end to end, from defining strategy and architecture through executing the plan, managing risks, and driving signoff without needing constant oversight\nYou can explain a verification bottleneck, a coverage gap, or a project risk to a design lead or program manager in two sentences without losing the technical nuance that matters\nYou combine strategic thinking with attention to detail, knowing when to zoom out to assess methodology and when to dive into a waveform to find the root cause\nYou mentor engineers by sharing not just what to do but how to think about verification problems, coverage strategies, and trade-offs in a way that builds their capability over time\nYou adapt quickly in evolving project environments, shifting priorities, and ambiguous requirements, and you help the team stay focused on what actually moves the needle toward delivery\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6753,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"visa":[],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.725,"p_room":0.45,"age_days":23,"expected_fill_days":14,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18308","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18308.json","meta":{"generated_at":"2026-10-20T09:44:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10674,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18308"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18308"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18308"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-18308\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18308"}]}