{"id":1311454,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18490","title":"ASIC Digital Design, Sr Staff Engineer-18490","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":75,"ghost_share":0.04,"stale_share":0,"repost_share":0.173,"time_to_fill_p50_days":15,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:33:20Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-22T02:05:46Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years working at the boundary between hardware and software, writing code that must configure real silicon, not just pass a test suite. You know that the difference between a PHY that trains reliably and one that fails intermittently often comes down to a register sequence you wrote three months ago, and you are the kind of engineer who thinks through those sequences before they become customer issues.\nYou are comfortable moving between C firmware that runs on embedded controllers and Python scripts that automate build flows. When a new feature lands from the design team, you do not wait for perfect documentation. You dig into RTL, ask the right questions, and figure out what the configuration software needs to do to make it work in the real world.\nDebugging is where you thrive. You have traced boot failures through firmware logs, register dumps, and waveform viewers enough times to know what good bring-up looks like and what smells wrong. You do not just fix the symptom; you understand the root cause and make sure it does not come back.\nAt Synopsys, you will work on DDR PHY IP that ships everything from data center servers to automotive SoCs. The team is small, the problems are hard, and what you build directly affects whether our customers' chips work on first silicon.\nWhat You'll Be Doing\nDesign, develop, and maintain PHYINIT, the configuration software that initializes and configures Synopsys DDR PHY IP across multiple product generations\nWrite runtime firmware that runs on embedded controllers within the PHY, managing training sequences, calibration, and operational modes\nCollaborate directly with digital design and verification engineers to enable new DDR features, translating RTL changes into working configuration code\nDebug PHY bring-up issues on customer silicon and internal test chips, analyzing register states, firmware logs, and waveforms to isolate root causes\nBuild and improve automation flows using Python or Perl to generate configuration code, validate settings, and streamline integration into customer SoCs\nOwn the software/firmware release process for PHYINIT, ensuring compatibility across design revisions and customer use cases\nParticipate in architecture discussions for future PHY generations, representing the software and firmware perspective early in the design cycle\nThe Impact You Will Have\nYour configuration software will determine whether DDR PHY IP integrates cleanly into customer designs or creates weeks of bring-up delays\nThe firmware you write will run on millions of chips across data center, mobile, automotive, and AI applications\nYour debugging work will directly reduce time to first silicon success for customers building next-generation systems\nThe automation flows you build will accelerate how quickly the team can validate new features and release to customers\nYour input on design decisions will shape how configurable and de-buggable future PHY generations are from day one\nThe quality of your code will affect how reliably high-speed memory interfaces train and operate in production systems\nYour collaboration with design and verification will close the loop between what the RTL does and what customers can use\nWhat You'll Need\nBachelor’s degree in electrical engineering, Computer Engineering, or equivalent practical experience\n5+ years of hands-on experience in ASIC design, verification, or firmware development, ideally involving configuration or bring-up work\nStrong C programming skills with experience writing firmware or embedded software for hardware systems\nSolid understanding of data structures, algorithms, and software design principles applied to hardware configuration problems\nProficiency in scripting languages like Python or Perl for automation, code generation, or build flows\nProven debugging skills across multiple layers, firmware, RTL, registers, and silicon behavior\nExperience with high-speed interface protocols such as DDR, LPDDR, or other memory standards is a strong plus\nWho You Are\nYou can read RTL well enough to understand what a configuration register does, not just what the spec says it should do\nYou write code that other engineers can debug six months later without needing you in the room\nWhen a bring-up fails, you methodically work through failure, checking assumptions and isolating variables instead of guessing\nYou communicate clearly with design engineers who think in Verilog and verification engineers who think in test benches, translating between their worlds and yours\nYou push back when a new feature is underspecified from a software perspective, and you do it early enough to matter\nYou are comfortable working across time zones with a global team, and you document your work in a way that makes asynchronous collaboration work\nThe Team You'll Be Part Of\nYou will join the DDR PHY IP team within Synopsys' Silicon Design & Verification business. This team builds the physical layer IP that enables high-speed memory interfaces in chips across every major market, from mobile to data center to automotive. The group is responsible for the full stack: analog design, digital design, verification, and the configuration software that ties it all together. Your work on PHYINIT will sit at the center of that stack, directly enabling how customers integrate and use the IP.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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