{"id":1311229,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18576","title":"ASIC Digital Design, Sr Staff Engineer - 18576","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":52000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-23T14:53:57Z","board_verified":true,"closed_at":null,"days_open":26,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":26},"description":"Job Description and Requirements\nJob Title:\nSr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent the better part of a decade verifying complex ASIC designs, and you know that the hardest bugs are the ones that hide in corner cases three layers deep in a protocol handshake. You have worked on memory interfaces long enough to know that HBM, DDR, and LPDDR are not just acronyms, they are ecosystems with timing constraints, power states, and failure modes that can sink a tapeout if you miss them.\nYou do not wait for a design to be \"ready\" before you start thinking about verification. You are already mapping out testbenches, coverage models, and corner cases while the RTL is still being written. When something does not make sense in a spec, you ask. When a test fails in a way that should not be possible, you dig until you find the root cause, not just a workaround.\nYou have built verification environments from scratch and you have also inherited messy ones and made them better. You know how to balance thoroughness with schedule pressure, and you can explain a coverage gap to an architect without making it feel like blame. At this point in your career, you are not just verifying designs, you are shaping how verification gets done, mentoring engineers, and setting the standard for what good looks like.\nWhat You'll Be Doing\nDesign and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM\nWrite detailed test plans that cover functional scenarios, corner cases, and protocol compliance for memory controller and interface IP designs\nDevelop reusable verification IP and testbenches that can be adapted across multiple projects and IP variants\nWork directly with design and architecture teams to identify bugs, clarify specifications, and close coverage gaps before tapeout\nRun functional coverage analysis, track metrics, and drive coverage closure across complex multi-protocol environments\nMentor junior verification engineers on UVM best practices, debugging techniques, and verification strategy\nUse simulation tools like VCS or ModelSim to execute regression suites, debug failures, and validate design changes\nThe Impact You Will Have\nDeliver Interface IP that powers memory subsystems in AI accelerators, mobile SoCs, and high-performance computing platforms used across the industry\nReduce post-silicon bugs and customer escalations by catching issues early through rigorous verification and coverage-driven testing\nShape the verification methodology and standards that the team will use for the next generation of memory IP products\nAccelerate project schedules by building reusable verification components that cut bring-up time on future designs\nRaise the technical bar across the verification team by mentoring engineers and sharing hard-won lessons from complex bring-ups\nContribute to the quality and reputation of Synopsys IP, which directly affects customer trust and product adoption\nHelp define what \"done\" means for verification, ensuring that coverage, corner cases, and compliance are never compromised under schedule pressure\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering or Computer Engineering with 6 to 8+ years of hands-on ASIC or SoC verification experience\nProven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs\nStrong proficiency in SystemVerilog and UVM, including building testbenches, writing assertions, and developing verification IP\nDeep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture\nExperience using simulation tools such as VCS, ModelSim, Xcelium, or equivalent in a regression and debug workflow\nDemonstrated ability to drive functional coverage closure and deliver fully verified IP on schedule\nExperience with HBM2, HBM3, DDR4, DDR5, LPDDR4, or LPDDR5 is a strong plus\nWho You Are\nYou can look at a failing test and quickly narrow down whether it is a testbench issue, a design bug, or a timing problem without burning a day in the debugger\nYou push back when a test plan is too shallow or a coverage model is missing a critical scenario, and you do it in a way that helps the team get better\nYou can explain a complex protocol violation to a design engineer in two sentences without losing the technical nuance\nYou are comfortable working across time zones and teams, coordinating with architects in one region and design engineers in another without losing momentum\nYou take ownership of the verification closure process and do not wait for someone else to tell you what needs to be done next\nYou mentor junior engineers by showing them how to think through a problem, not just how to fix the immediate issue in front of them\nThe Team You'll Be Part Of\nYou will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next generation technologies.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6290,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"visa":[],"liveness":{"score":31,"band":"fade","label":"Fading","p_open":1,"p_active":0.689,"p_room":0.45,"age_days":26,"expected_fill_days":15,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18576","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18576.json","meta":{"generated_at":"2026-10-23T16:13:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24589,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18576"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18576"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18576"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-18576\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18576"}]}