{"id":1311352,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18636","title":"ASIC Digital Design, Sr Staff Engineer - 18636","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":47000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-25T18:21:16Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"Job Description and Requirements\nAlternate Job Titles\nDigital Verification Senior StaffEngineer\nMixed-Signal PHY Verification Lead\nASIC Verification Sr Staff Engineer\nRTL/GLS Verification Senior StaffEngineer\nHigh-Speed Interface Verification Senior StaffEngineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the verification trenches where the difference between a clean tapeoutand a respincomes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.\nWhat You'll Be Doing\nDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteria\nPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments\nBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks\nGenerate VCD files and run power analysis using PrimeTimePX, correlating simulation activity with power consumption\nDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes\nCollaborate with design, analog, and integration teams to align verification strategy with IP architecture\nReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close them\nThe Impact You Will Have\nCatch critical bugs before tapeout, preventing costly respinsand protecting customer schedules\nEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocks\nImprove verification quality across the team by building reusable test components and coverage models\nProvide early feedback to design teams on corner cases, timing issues, and power anomalies\nSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage ranges\nStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIe\nReduce post-silicon debug cycles by catching gate-level and power issues during simulation\nWhat You'll Need\n5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debugging\nDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLS\nProficiency in SystemVerilogand experience working within UVM-based verification environments\nStrong debugging skills across waveform analysis, coverage review, and simulation log interpretation\nExperience with power analysis tools such as PrimeTimePX, including VCD generation\nKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plus\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience\nWho You Are\nYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slides\nYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gaps\nYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precision\nYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixes\nYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussions\nThe Team You'll Be Part Of\nYou will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5709,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.701,"p_room":0.45,"age_days":28,"expected_fill_days":15,"reasons":["conf:3","velocity","win:tail","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18636","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-18636.json","meta":{"generated_at":"2026-10-25T20:18:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28765,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18636"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18636"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18636"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-18636\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-18636"}]}