{"id":3432035,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-19066-2","title":"ASIC Digital Design, Sr Staff Engineer - 19066","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":73,"ghost_share":0.055,"stale_share":0,"repost_share":0.205,"time_to_fill_p50_days":15,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boxborough, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-29T00:58:27Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-10-31T01:23:40Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nWe Are\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We lead in chip design, verification, and IP integration, empowering innovators to create high-performance silicon and software solutions. Join us and help shape the future of technology.\nYou Are\nA highly experienced design verification engineer with deep expertise in verifying complex digital IP and high-speed interfaces. You bring strong experience in SystemVerilog, UVM, coverage-driven verification, and debug, along with knowledge of technologies such as DDR, UCIe, PHY, or SERDES. You thrive on solving complex verification challenges and driving high-quality IP from initial architecture through verification closure.\nWhat You’ll Be Doing\nDevelop and execute verification strategies for PHY, DDRIO, UCIe, and other high-speed interface IP.\nArchitect and develop SystemVerilog/UVM testbenches, verification environments, test plans, and reusable verification components.\nCreate directed and constrained-random tests, assertions, functional coverage, and coverage models.\nDrive functional and code coverage closure, regression analysis, and verification signoff.\nDebug complex RTL, protocol, testbench, and system-level issues in partnership with design engineers.\nVerify block- and subsystem-level functionality, including interfaces, resets, clocking, low-power behavior, and error scenarios.\nCollaborate closely with RTL design, architecture, firmware, modeling, and implementation teams.\nMentor engineers and help drive verification methodology and best practices.\nThe Impact You Will Have\nEnsure the quality and robustness of next-generation high-speed connectivity IP.\nIdentify complex functional and protocol issues early in the development cycle.\nImprove verification efficiency, coverage, reuse, and overall product quality.\nContribute to industry-leading PHY and interface IP used in advanced semiconductor products.\nStrengthen verification methodologies and technical expertise across the engineering organization.\nWhat You’ll Need\nRequired Qualifications\nBS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.\nStrong experience in ASIC/IP design verification.\nAdvanced proficiency with SystemVerilog and UVM.\nExperience developing verification environments, test plans, assertions, functional coverage, and constrained-random tests.\nStrong RTL and waveform debugging skills.\nExperience with PHY, DDR/DDRIO, UCIe, SERDES, PCIe, CXL, or similar high-speed interface technologies.\nUnderstanding of the complete ASIC/IP development and verification lifecycle.\nStrong analytical, problem-solving, and communication skills.\nPreferred Qualifications\nExperience verifying complex IP at the block and subsystem level.\nExperience with coverage-driven verification and verification closure.\nFamiliarity with low-power verification, clock/reset verification, and protocol checking.\nExperience with industry-standard simulation, debug, coverage, and verification tools.\nExperience mentoring engineers or providing technical verification leadership.\nWho You Are\nA verification engineer who enjoys finding difficult corner cases before they become silicon issues.\nA strong debugger who can work across RTL, testbench, protocol, and system boundaries.\nA collaborative technical partner to design and architecture teams.\nA self-starter who can independently drive verification from planning through closure.\nA mentor who raises the technical capability of the broader team.\nThe Team You’ll Be A Part Of\nYou will join a team developing next-generation PHY and high-speed interface IP. Working closely with architecture, RTL design, verification, and implementation teams, you will help ensure complex IP meets demanding functional, performance, and quality requirements.\nRewards and Benefits\nSynopsys offers a comprehensive and competitive benefits package designed to support your health, wellbeing, and financial future. Your recruiter can provide additional details regarding compensation, benefits, and total rewards during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.","description_format":"text","description_chars":5095,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-29T00:58:27Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 178 · green card filings: 177","filings_12m":178,"filings_prev_12m":208,"green_card_filings_12m":177,"median_offered_wage_usd":157472,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":61},{"country":"GB","licensed_sponsor":true,"evidence":"Licensed UK visa sponsor (Skilled Worker)","filings_12m":null,"filings_prev_12m":null,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Skilled Worker","cap_exempt":false,"checked_at":"2026-10-30T06:20:16+00:00","sources":["UK Home Office: register of licensed sponsors (workers)"],"filings_for_role_12m":0}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":15,"reasons":["conf:2","velocity","win:early","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-19066-2","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-19066-2.json","meta":{"generated_at":"2026-10-31T05:03:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7170,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-19066-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-19066-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-19066-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-19066-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-19066-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3432035}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3432035},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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