{"id":2460892,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-2","title":"ASIC Digital Design, Sr Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-13T17:19:13Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-14T14:14:57Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nASIC Verification Engineer, Staff\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to advanced learning machines. As the global leader in EDA tools, semiconductor IP, and silicon engineering solutions, we empower the creation of the world’s most advanced chips across AI/ML, high-performance computing, automotive, cloud, and mobile applications. Within our division, we develop and deliver interface subsystems that power industry-leading SoCs. Join us to transform the future through continuous technological innovation and world-class engineering excellence.\nYou Are:\nYou are an enthusiastic engineer who thrives at the intersection of various interface IPs. Your analytical mindset and collaborative spirit drive you to solve complex technical challenges that shape the future of connectivity. You are passionate about deepening your expertise and excited by the opportunity to work on advanced DDR/HBM/PCIe/UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs. You value technical mastery, teamwork, mentorship, and the continuous pursuit of innovation. Your curiosity leads you to understand diverse interface IPs, and you ensure the highest standards of silicon performance through meticulous attention to detail. Navigating simulation environments and debugging challenging issues is second nature to you, and you excel at collaborating with teams across the globe.\nWhat You’ll Be Doing:\nTechnically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.\nDefining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality.\nSpecifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models\nCoding and debugging test cases, including the creation of complex checkers and assertions using System Verilog/UVM.\nExtracting and reviewing functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.\nManaging regressions and contributing to the continuous improvement of verification strategies and test environments.\nDebugging and resolving simulation failures, ensuring root-cause analysis and timely solutions.\nWorking closely with RTL designers and architects to ensure functional correctness.\nThe Impact You Will Have:\nDrive quality that powers AI, automotive, cloud, and mobile applications at massive scale.\nAdvance the state-of-the-art in AI assisted verification methodologies, influencing future verification flows and processes.\nContribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.\nCollaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.\nBolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.\nWhat You’ll Need:\nBachelor's or Master's degree in electronics/electrical engineering or related field, with 8+ years’ experience in ASIC/FPGA Verification.\nAbility to debug and define robust verification strategies; experience mentoring is a plus for senior candidates.\nDemonstrated experience in technically leading a team, record of successful collaboration and stakeholder management.\nProven expertise in developing System Verilog/UVM based test environments for complex ASIC designs.\nAdvanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests.\nStrong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.\nExperience with interface protocols and IP design/verification processes; knowledge of DDR/HBM/PCIe/UCIe/Ethernet/UALink is highly desirable.\nHands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.\nWho You Are:\nAnalytical and detail-oriented, with strong problem-solving and debugging skills.\nInitiative-taking and driven to deliver high-quality results in a fast-paced environment.\nSeeking feedback, sharing knowledge, and mentoring others when possible.\nCollaborative leader who inspires and mentors team members to achieve their best.\nAnalytical thinker with strong critical thinking skills and a commitment to quality.\nExceptional communicator, able to bridge technical and non-technical stakeholders.\nSelf-motivated and proactive, with a passion for continuous learning and professional development.\nAdaptable and resilient in the face of complex challenges and changing priorities.\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5534,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning","Professional development"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-13T17:19:13Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":12,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-2","json_url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-2.json","meta":{"generated_at":"2026-10-14T15:37:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"assistant_verified","counted_by":"address","units_charged":1,"used_today":3055,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-sr-staff-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-sr-staff-engineer-2"}]}