{"id":2841397,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-3","title":"ASIC Digital Design, Sr Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":73,"ghost_share":0.055,"stale_share":0,"repost_share":0.205,"time_to_fill_p50_days":15,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":51000,"max_usd":107000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-19T09:05:53Z","employer_posted_date":"2026-10-19","last_verified_at":"2026-10-30T21:06:36Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":11},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou’re an accomplished ASIC Digital Design Verification expert with 10+ years of experience, skilled in UVM environments and passionate about building reliable, high-performance chips. You’re a hands-on leader and mentor, eager to leverage AI tools, formal verification, and the latest methodologies.Your collaborative spirit, analytical mindset, and \"can do\" attitude drive your success in fast-paced, innovative environments.\nWhat You’ll Be Doing:\n* Leading the verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.\n* Partnering with design teams to define verification requirements\n* Building and maintaining UVM testbenches and agents\n* Reviewing and improving test plans and code\n* Applying SVA and formal verification techniques\n* Developing and executing comprehensive test plans to verify the functionality and performance of your designs.\n* Implementing and analyzing coverage metrics\n* Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.\n* Staying up-to-date with the latest industry trends and technologies, continuously improving your skills and knowledge.\nThe Impact You Will Have:\n* Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.\n* Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.\n* Enhancing the overall quality and performance of Synopsys' products through meticulous design and verification processes.\n* Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.\n* Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.\n* Contributing to Synopsys' reputation as a leader in the semiconductor industry through your expertise and innovative solutions.\nWhat You’ll Need:\n* Extensive experience in ASIC digital design and verification. Background in RTL design is preferred.\n* 10+ years in ASIC/UVM verification\n* SystemVerilog,C, Python, TCL/Perl proficiency\n* Proficiency in using industry-standard EDA tools and methodologies for verification.\n* Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC designs.\n* Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.\n* Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.\nWho You Are:\n* A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.\n* A strategic thinker with the ability to implement goals that have a direct impact on department results.\n* A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.\n* A collaborative team player who thrives in dynamic and fast-paced environments.\n* A lifelong learner who stays up to datewith the latest industry trends and continuously seeks to improve their skills and knowledge.\nThe Team You’ll Be A Part Of:\nYou will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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