{"id":3368580,"url":"https://alion.io/job/synopsys-asic-digital-design-sr-staff-engineer-4","title":"ASIC Digital Design, Sr Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":73,"ghost_share":0.055,"stale_share":0,"repost_share":0.205,"time_to_fill_p50_days":15,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":143000,"max_usd":264000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimePower","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"Synopsys VC Formal","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-28T00:03:24Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-31T01:23:40Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Description and Requirements\nAbout the Role\nWe are seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off. You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design.\nWhat You'll Be Doing:\nDrive front-end sign-off: static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design.\nTranslate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems.\nOwn timing constraint (SDC) development and review; support full-chip timing closure.\nPerform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.\nApply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior.\nRun power estimation and analysis (PrimePower) and feed findings back into RTL optimization.\nContribute to methodology improvement, scripting, and regression automation.\nWhat You'll Need:\nBS/MS in Electrical/Computer Engineering or a related field, with 8+ years of experience in ASIC design and STA sign-off.\nDemonstrated experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.\nStrong proficiency in SystemVerilog/Verilog RTL coding for synthesis.\nSolid understanding of synthesis (Design Compiler / Fusion Compiler) and QoR analysis.\nExperience with low-power design techniques: clock gating, power gating, multi-Vt, UPF.\nWorking knowledge of SDC constraint development and timing closure methodology\nProficiency in scripting: TCL, Python, Perl, and Linux/UNIX environments.\nCommand of digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB).\nHigh-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI)\nThe Impact You Will Have:\nThe quality of your RTL and sign-off discipline will shape how well our designs meet their performance, power, and area goals.\nClean front-end sign-off from you means fewer late-stage surprises, fewer ECO cycles, and a predictable path to tape-out.\nThe methodology and automation you build will raise the quality bar for every future project the team takes on.\nYour work ships in HPC and AI accelerator silicon deployed at scale in data centers worldwide.\nWho You Are:\nCurious and improvement-minded: You identify an inefficient workflow, which you then automate and turn it into a reusable capability for everyone.\nAccountable and proactive: You are hands-on and take the lead and responsibility for driving issues to a closure.\nA clear communicator: Your specifications, review feedback, and sign-off documentation provide clear guidance for stakeholders.\nHighly detail-oriented: You follow quality and sign-off checklists rigorously and prioritize finding issues early in the process than at a later stage. #LI-NK4\n\nThe Team You’ll Be A Part Of:\nYou’ll join a collaborative ASIC Digital Design team focused on delivering high-performance, reliable solutions through close partnership across analog, physical design, and applications engineering.\nRewards and Benefits:\nSynopsys offers a comprehensive package of health, wellness, financial, and professional development benefits designed to support you throughout your career. #LI-NK4\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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