{"id":2328814,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18270","title":"ASIC Digital Design, Staff Engineer - 18270","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":55000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Copilot","optional":false},{"name":"Cursor","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-12T08:17:31Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-24T12:15:04Z","board_verified":true,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have built verification environments that catch bugs before they become customer issues. Whether you have been doing this for three years or closer to ten, you have learned that verification is not about running tests; it is about thinking through what could go wrong and building the infrastructure to prove it won't. You understand that a well-written testbench is half the battle, and the remaining is knowing which corner cases matter, and which ones are just noise.\nYou are comfortable working in System Verilog and UVM, writing test cases that exercise real scenarios, not just the ones in the specification. You have debugged enough simulations to recognize patterns in waveforms, and you know when to dig deeper versus when to loop in the design team. Protocols like MIPI UFS/UniPro, DDR, PCIe, Ethernet or USB are not just acronyms to you; you have worked with at least one of them closely enough to understand how transactions flow and where things typically break.\nWorking on a verification team means asking questions when the test plan does not make sense, writing assertions that catch issues, and tracking coverage in a way that tells you what you have validated and what you have not. At Synopsys, you will work on IP cores that go into AI systems, automotive platforms, and data centers. The verification work you do will determine whether that IP works when it ships.\nWhat You'll Be Doing\nBuild and maintain UVM-based testbench for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors\nWrite System Verilog test cases and constrained random stimulus to verify functional correctness across different operating modes and protocol scenarios\nDevelop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals\nDebug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes\nImplement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation\nCollaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations\nRun regressions, analyze results, and work toward coverage closure, documenting verification status and outstanding issues\nThe Impact You Will Have\nEnsure Synopsys IP cores are thoroughly validated before they reach customers building AI accelerators, automotive systems, and cloud infrastructure\nReduce post-silicon bugs and customer escalations by catching design issues early through systematic verification and coverage analysis\nContribute to faster IP release cycles by building reusable verification components and efficient test strategies\nHelp maintain high-quality standards across Synopsys IP products, directly impacting customer success and product reliability\nSupport the development of verification best practices and methodologies within the Bangalore team\nEnable design teams to iterate faster by providing clear, actionable feedback on functional correctness and edge case behavior\nBuild verification infrastructure that can scale across multiple IP variants and protocol configurations\nWhat You'll Need\n4-8 years of hands-on experience in ASIC or RTL verification for IP cores or digital designs\nUnderstanding of verification planning, test case development, and coverage-driven verification concepts\nWorking knowledge of UVM or similar verification methodologies, with experience building testbench components and writing test cases\nSolid System Verilog skills, including understanding of constrained random verification, coverage, and assertions\nFamiliarity with at least one industry-standard protocol such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, USB or similar\nExperience debugging RTL simulations using waveform viewers and analyzing coverage reports to guide verification progress\nExperience with Perforce or similar revision control environment\nBasic scripting ability in Python, Perl, TCL, or shell scripting to support automation and regression management\nAbility to use AI tools like Cursor and GitHub Copilot for analysis, development, debugs and maximizing productivity.\nHave good communication skills, will be a team player, and will have good problem-solving skills.\nWho You Are\nYou can look at a design spec and start listing the test scenarios that need to be covered without waiting for someone to hand you a complete test plan\nYou are methodical about debugging, when a test fails, you do not guess, you trace through the waveform and log until you understand exactly what happened\nYou ask questions when requirements are unclear or when a design decision seems like it will be hard to verify, and you do it early enough to matter\nYou are comfortable working with design engineers who may be in different locations, coordinating on bug fixes, clarifications, and verification scope\nYou track your own coverage and verification progress, knowing what has been tested, what has not, and what the gaps mean for overall quality\nYou are motivated by the moment when your testbench catches a real bug, the kind that would have caused problems downstream if it had slipped through\nThe Team You'll Be Part Of\nYou will join the IPG and SSG Group at the Bangalore Design Center, working alongside verification and design engineers who develop IP cores for a range of applications including AI, automotive, and cloud infrastructure. The team collaborates across Synopsys' global sites, and you will have the opportunity to work on IP that goes into high-performance systems used by customers worldwide.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6720,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-12T08:17:31Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.836,"p_room":0.75,"age_days":11,"expected_fill_days":15,"reasons":["conf:2","velocity","win:late","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18270","json_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18270.json","meta":{"generated_at":"2026-10-24T14:13:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20451,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18270"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18270"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18270"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-staff-engineer-18270\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18270"}]}