ASIC Digital Design, Staff Engineer - 18436

Job Description and Requirements

Alternate Job Titles

• Design Verification Engineer
• Digital Verification Engineer
• RTL Verification Engineer
• IP Verification Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years proving that silicon actually worksthe way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeoutinto a respin, and building the infrastructure to catch those problems before they become expensive.

You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually firewhen something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.

Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.

At Synopsys, you will work on IP that powers the chips inside the deviceschanging how the world connects, computes, and moves.

What You'll Be Doing

• Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure
• Write test cases, assertions, and checkers in SystemVerilogto ensure comprehensive functional coverage
• Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi
• Drive coverage analysis and closure across code, functional, and assertion metrics
• Participate in technical and peer reviews to ensure verification quality and process adherence
• Collaborate with design, architecture, and silicon validation teams to identify and resolve issues early

The Impact You Will Have

• Ensure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applications
• Reduce costly respinsand post-silicon debug cycles by catching critical bugs early through rigorous verification
• Contribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliability
• Enable faster time-to-market for customers building next-generation chips by delivering proven, validated IP
• Strengthen verification methodologies that scale across global engineering teams
• Mentor and elevate the skills of the Vietnam engineering team through knowledge sharing

What You'll Need

• Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field
• 2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP
• Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies
• Experience with VCS and Verdi for simulation and debug
• Solid understanding of verification planning, coverage-driven verification, and assertion-based verification
• Familiarity with formal verification tools like vc_formalis a plus
• Scripting experience in Perl, TCL, or Python is a plus

Who You Are

• You approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptom
• You can explain a complex verification failure to a design engineer in a way that gets them to the fix faster
• You are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestone
• You thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being asked
• You communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan

The Team You'll Be Part Of

You will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.