{"id":2431821,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18564","title":"ASIC Digital Design, Staff Engineer - 18564","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":76,"ghost_share":0.039,"stale_share":0,"repost_share":0.171,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":52000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T09:21:34Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-22T16:34:25Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years in the space where analog meets digital, and you know that the hardest bugs live at that boundary. You understand that mixed-signal verification is not just about running simulations, it is about building the methodology that catches the corner case three months before tapeout. You think in test plans, coverage models, and debug strategies that actually close, not just look good in a review.\nYou are comfortable sitting with an analog designer to understand a bias circuit, then walking back to your desk to model its behavior in Verilog-A and build a UVM environment around it. You do not wait for perfect specs. You ask the right questions, build what you need, and move forward while others are still debating the approach.\nYou have owned verification sign-off before. You know what it takes to get from \"mostly working\" to \"ready to tape out,\" and you have the scars to prove it. When a simulation fails at 3am in a regression, you are the one who can read the waveform, trace it back through the analog-digital handshake, and know exactly where to look.\nAt Synopsys, you will work on complex mixed-signal IP that powers the semiconductor industry. The problems are real, the stakes are high, and what you verify actually ships.\nWhat You'll Be Doing\nOwn end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects\nBuild and maintain UVM/SystemVerilog verification environments that integrate seamlessly with Verilog-A, Verilog-AMS behavioral models, and mixed-signal simulators\nDebug complex analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS-specific debug tools\nDevelop assertions, monitors, scoreboards, and automated verification infrastructure that catch real bugs, not just check boxes\nDrive AMS simulation efficiency improvements, optimize regression flows, and reduce debug turnaround time across the verification pipeline\nCollaborate daily with analog designers, digital verification engineers, modeling teams, and architecture groups to align verification approach with design intent\nMentor verification engineers on AMS methodology, review test plans and environments, and drive best practices across the team\nThe Impact You Will Have\nYour verification methodology will directly determine whether complex mixed-signal IP tapes out on schedule or slips by months\nThe coverage models and test scenarios you define will catch silicon bugs before they become expensive respins\nYour automation and regression infrastructure will cut verification cycle time and let the team move faster without sacrificing quality\nThe debug frameworks you build will make it possible for junior engineers to solve problems that used to require senior intervention\nYour technical leadership will shape how the team approaches AMS verification on future projects, raising the bar across the organization\nThe behavioral models and monitors you create will be reused across multiple IP families, multiplying your impact beyond a single project\nYour collaboration with analog and digital teams will close the gaps that typically cause late-stage integration failures\nWhat You'll Need\n5+ years of hands-on experience in AMS verification, with a proven track record of owning verification sign-off for mixed-signal designs\nExpert-level proficiency in SystemVerilog and UVM, with deep understanding of testbench architecture, coverage-driven verification, and constrained-random methodologies\nStrong working knowledge of Verilog-A and Verilog-AMS for behavioral modeling and mixed-signal simulation\nSolid understanding of analog circuit behavior, including bias circuits, regulators, PLLs, ADCs, DACs, or other mixed-signal blocks\nExperience with AMS simulators (Spectre AMS, Xcelium AMS, or similar) and waveform debug tools for mixed-signal analysis\nStrong scripting skills in Python, Perl, or Tcl for automation, regression management, and infrastructure development\nExperience with AI/ML-based verification techniques or automation frameworks is a strong plus\nWho You Are\nYou can walk into a design review, absorb the analog designer's intent, and walk out with a verification plan that actually tests what matters, not just what is easy to code\nYou push back when a test plan is too shallow or a coverage model misses a critical corner case, and you do it in a way that moves the conversation forward\nYou are the person the team comes to when a regression is failing in a way that makes no sense, because you know how to read a mixed-signal waveform and trace the problem back to its source\nYou do not need someone to tell you what to automate, you see the repetitive, error-prone work and you build the tooling to eliminate it\nYou mentor by showing, not just telling, you review code, pair on tough debug sessions, and leave people better at their job than they were before\nYou are organized enough to manage verification across multiple blocks in parallel and technical enough to dive deep when something does not add up\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6276,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-13T09:21:34Z"}],"visa":[],"liveness":{"score":75,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.829,"p_room":0.9,"age_days":8,"expected_fill_days":15,"reasons":["conf:1","velocity","win:mid","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18564","json_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18564.json","meta":{"generated_at":"2026-10-22T19:48:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3337,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18564"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18564"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18564"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-staff-engineer-18564\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18564"}]}