{"id":3121688,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18782","title":"ASIC Digital Design, Staff Engineer-18782","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":98,"open_postings":67,"ghost_share":0.06,"stale_share":0,"repost_share":0.239,"time_to_fill_p50_days":17,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":30000,"max_usd":63000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-23T00:42:45Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-11-03T11:15:50Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":11},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and technically adept engineer who thrives in a fast-paced, collaborative environment. With a strong background in digital design and verification, you possess an in-depth understanding of RTL-based IP core development, particularly for high-speed memory interfaces such as HBM. You are driven by curiosity and innovation, eager to tackle complex challenges in the semiconductor industry. Your experience enables you to make informed architectural decisions, and you are comfortable working autonomously while also excelling as a team player. You communicate clearly-both in English and within multicultural, cross-functional teams-and are always looking for opportunities to mentor, lead, and drive technical excellence.\nYou approach problems with creativity and rigor, breaking down large tasks into actionable plans. Your strong analytical mindset, combined with attention to detail, ensures that your designs and verification strategies are robust and scalable. You are excited about working on products that power AI, automotive, data centers, and next-generation computing platforms. You stay up-to-date with industry trends, tools, and methodologies, and are motivated by continuous learning and professional growth. Your proactive attitude, adaptability, and resilience make you a valued contributor and trusted colleague within any high-performance engineering team.\n仕事内容\n最新のSoC向けHBMコントローラIPのRTL設計・実装を担当します。\n仕様書をもとに詳細なマイクロアーキテクチャを設計します。\n設計や検証の判断や方針決定、検証計画の策定、テストベンチの構築（SystemVerilog/UVM使用）を行います。\n設計レビューをリードし、グローバルチームと連携します。\n若手エンジニアの指導や、進捗・検証レポートの作成も担当します。\n期待される成果\n高品質なHBMコントローラIPを提供し、AIや自動車、サーバーなど幅広い分野で活躍します。\n製品の性能向上や統合リスクの低減に貢献し、技術力を高めます。\nチーム全体の技術向上やベストプラクティスを推進します。\n必要なスキル・経験\nRTL設計やマイクロアーキテクチャ設計の経験\nUVM/VMM/OVMなどの検証手法やSystemVerilogの知識\nSoC/ASIC設計フローや検証計画、カバレッジ重視の検証経験\nシミュレーションツール、Unix環境、スクリプト言語（Perl, Python, TCL）\nDDR、PCIE、AXI/CHI、SD/eMMC、Ethernet、USB、MIPIなどのプロトコル知識\n英語でのコミュニケーション能力\nBSEE（9年以上）またはMSEE（7年以上）の実務経験\n歓迎スキル\nフォーマル検証、ファームウェア・組込みソフト、C/C++、機能安全（ISO26262, FMEDA）経験\nWhat You’ll Be Doing:\nDesigning and implementing RTL-based HBM controller IP cores for cutting-edge SoC applications.\nInterpreting and translating standard and product functional specifications into detailed micro-architectures.\nMaking architectural and methodological judgments for both design and verification activities.\nDeveloping comprehensive verification strategies, including testbench architectures using SystemVerilog and UVM.\nCreating and maintaining verification plans, item lists, coverage metrics, and checker definitions to ensure thorough validation.\nCoordinating and leading design review meetings to ensure alignment and technical excellence across global teams.\nProviding technical leadership and mentoring to junior engineers, setting quality standards and driving innovation.\nDocumenting progress, generating reports with “visible” verification metrics, and ensuring project milestones are met.\nThe Impact You Will Have:\nDelivering high-quality, robust HBM controller IP that accelerates time-to-market for Synopsys customers.\nEnabling key innovations for AI, automotive, server, and data center applications through advanced memory interface solutions.\nReducing integration risk and enhancing system performance for a broad portfolio of end-customer products.\nDriving technical excellence and best practices across global, cross-functional engineering teams.\nSupporting Synopsys’ reputation as a leader in silicon IP by ensuring products meet and exceed industry standards.\nContributing to continuous improvement by identifying and implementing process, methodology, and tool enhancements.\nMentoring and developing the next generation of engineering talent within Synopsys.\nWhat You’ll Need:\nExtensive hands-on experience with RTL design and micro-architecture development from functional specifications.\nProficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.\nDeep understanding of SoC/ASIC design flows, verification planning, and coverage-driven verification.\nExperience with simulation tools, Unix operating environments, and scripting languages (Perl, Python, TCL).\nSolid knowledge of protocols such as DDR, PCIE, AMBA (AXI/CHI), SD/eMMC, Ethernet, USB, and MIPI.\nStrong English communication skills and the ability to document and present technical concepts effectively.\nBSEE with 9~10+ years or MSEE with 7~12+ years of relevant experience.\nAdvantageous: Experience with formal verification, firmware/embedded software, C/C++, and functional safety standards (ISO26262, FMEDA).\nWho You Are:\nInnovative, self-motivated, and able to work independently with precision.\nExceptional problem-solving skills and keen attention to detail.\nEffective communicator and active listener, adept at cross-functional collaboration.\nTeam-oriented and supportive, with a willingness to mentor and share knowledge.\nAdaptable to new challenges, tools, and methodologies in a dynamic environment.\nCommitted to continuous learning and professional development.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5772,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"Japanese","level":"Advanced (C1)","optional":false},{"language":"English","level":"Upper-Intermediate (B2)","optional":false}]},"benefits":["Continuous learning","Professional development"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-23T00:42:45Z"}],"visa":[],"liveness":{"score":79,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.883,"p_room":0.9,"age_days":11,"expected_fill_days":17,"reasons":["conf:3","velocity","win:mid","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18782","json_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-18782.json","meta":{"generated_at":"2026-11-03T14:31:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20430,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18782"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18782"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18782"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-staff-engineer-18782\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-staff-engineer-18782"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3121688}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3121688},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}