{"id":1950246,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-19012","title":"ASIC Digital Design, Staff Engineer - 19012","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":79,"ghost_share":0.038,"stale_share":0,"repost_share":0.19,"time_to_fill_p50_days":14,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-06T09:38:49Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-20T12:46:01Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years verifying IP that has to work in silicon, not just pass regression. The difference between a clean tape-out and a respin often comes down to the corner case you caught at 2 AM in a Verdi waveform, and you are the engineer who finds it before it becomes a silicon bug. You read protocol specs the way some people read novels. UFS, UniPro, MIPI M-PHY are not just acronyms to you, they are systems you understand at the transaction level, the state machine level, and the timing level. You know where the edge cases hide.\nBuilding a UVM environment from scratch does not intimidate you. Neither does inheriting someone else's testbench and making it better. You write sequences that stress the design in ways the spec did not explicitly call out because you have learned that is where the bugs live. Coverage closure is not a checkbox exercise for you, it is a conversation with the design about what actually matters.\nYou do not need someone to tell you what to verify next. You read the spec, talk to the designer, look at the waveform, and figure it out. At Synopsys, you will work on high-speed interconnect IP that powers real products, and what you verify will ship.\nWhat You'll Be Doing\nOwn end-to-end verification for MphyV6, UFS, and UniPro IP blocks, from test planning through coverage closure and sign-off\nBuild and extend UVM testbenches in SystemVerilog, including agents, sequences, scoreboards, coverage models, and protocol checkers\nWrite constrained-random and directed tests that expose corner cases, protocol violations, and timing edge conditions\nDebug complex failures using Verdi at the waveform, transaction, and protocol level, performing root-cause analysis on RTL and testbench issues\nTranslate protocol specifications into executable test plans, SystemVerilog assertions, and functional coverage models\nCollaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and tape-out readiness\nMentor junior verification engineers through code reviews, debug sessions, and technical guidance on UVM best practices\nThe Impact You Will Have\nCatch silicon bugs before tape-out, directly reducing respin risk and time-to-market for high-speed interconnect IP used across the industry\nDeliver verified, production-quality IP blocks that meet protocol compliance and performance requirements for customer integrations\nBuild reusable verification infrastructure that accelerates future IP development and improves regression quality across the team\nDrive coverage closure strategies that focus verification effort where it matters, not just where it is easy to measure\nInfluence design decisions early by identifying architectural risks and edge cases during specification review\nStrengthen the technical capability of the verification team through mentorship, documentation, and knowledge transfer\nContribute to first-silicon success by ensuring verification completeness and clear handoff to validation teams\nWhat You'll Need\nBachelor's with 5+ years or Master's with 3+ years in Electronics Engineering, Computer Engineering, or equivalent technical discipline\nHands-on ASIC verification experience with ownership of IP or subsystem-level blocks\nDeep expertise in UVM methodology and SystemVerilog, including testbench architecture, constrained-random verification, and coverage-driven verification\nStrong working knowledge of high-speed protocol standards such as UFS, UniPro, MIPI M-PHY, PCiE, or similar interconnect protocols\nProficiency with Verdi for waveform debug, transaction-level analysis, and protocol visualization\nExperience writing SystemVerilog assertions and building functional and code coverage models\nDemonstrated ability to work independently, drive verification closure, and communicate technical issues clearly across teams\nWho You Are\nYou can look at a failing regression, open Verdi, and within an hour tell the team whether it is an RTL bug, a testbench race, or a protocol misunderstanding\nYou push back when a test plan is too vague or a coverage metric does not actually measure the risk it claims to address\nAmbiguity does not stop you. When the spec is unclear or the design is still evolving, you make reasonable assumptions, document them, and keep moving\nYou explain complex protocol behavior to designers and architects in a way that gets to the issue without requiring them to read 200 pages of specification\nMentoring junior engineers is not a distraction for you. You see it as part of building a team that can verify harder problems faster\nYou care about the quality of your testbench code as much as you care about the quality of the RTL you are verifying\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5855,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-06T09:38:49Z"}],"visa":[],"liveness":{"score":59,"band":"ok","label":"Likely open","p_open":1,"p_active":0.79,"p_room":0.75,"age_days":13,"expected_fill_days":14,"reasons":["conf:1","velocity","win:late","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-19012","json_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-19012.json","meta":{"generated_at":"2026-10-20T14:07:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15812,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-staff-engineer-19012"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-staff-engineer-19012"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-staff-engineer-19012"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-staff-engineer-19012\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-staff-engineer-19012"}]}