{"id":4139692,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-19220","title":"ASIC Digital Design, Staff Engineer - 19220","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Da Nang, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-12T04:56:07Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T10:24:48Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAlternate Job Titles:\nStaff RTL Design Engineer\nSenior Digital Design Engineer\nASIC RTL Engineer\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an experienced RTL designer eager to lead, innovate, and collaborate. You bring strong technical skills and a passion for high-speed memory and interface solutions. You excel at problem-solving, clear communication, and thrive in a team environment. Your experience covers the full silicon development flow, and you’re excited to make a tangible impact on advanced test chip projects.\nWhat You’ll Be Doing:\nDesigning and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog.\nCollaborating with analog and mixed-signal teams.\nAutomating workflows with scripting languages.\nDebugging complex hardware issues in lab bring-up and validation.\nDocumenting specifications and processes.\nDriving improvements in design and DFT/DFM flows.\nThe Impact You Will Have:\nDelivering reliable, high-speed memory IP for next-gen platforms.\nSupporting rapid customer time-to-market.\nEnhancing testchip team capabilities and innovation.\nMentoring and sharing expertise with peers.\nEnsuring product quality through robust verification.\nPromoting a collaborative, learning-focused culture.\nWhat You’ll Need:\n6+ years in RTL design/verification (SystemVerilog/Verilog).\nExperience with high-speed interfaces (DDR/HBM preferred).\nSkill in scripting (Python, Perl, Tcl, Shell).\nKnowledge of ASIC/IP flows and DFT/DFM.\nExperience debugging complex hardware issues.\nWho You Are:\nClear communicator and team player.\nAnalytical, proactive, and adaptable.\nOpen to learning and mentoring.\nThe Team You’ll Be A Part Of:\nJoin our expert testchip team in Ho Chi Minh City, collaborating across digital, analog, and mixed-signal domains to deliver industry-leading memory interface solutions.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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