{"id":4268637,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-19511","title":"ASIC Digital Design, Staff Engineer - 19511","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-13T17:05:13Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T17:05:13Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years designing RTL that ships in real products, not just passes verification. You know that the difference between a design that meets timing at 800MHz and one that barely scrapes by at 600MHz is a hundred small decisions made during architecture, and you are the kind of engineer who makes those decisions deliberately. You think in trade-offs, area versus latency versus throughput, and you can articulate why you chose one path over another without needing to defend it.\nYou are comfortable moving between high-level architecture discussions and deep RTL debugging. When someone hands you a 300-page IEEE spec, you do not get overwhelmed. You pull out what matters, sketch the datapath, identify the bottlenecks, and start building. You have written enough Verilog to know when a design is going to cause problems in synthesis before you even run the tool.\nYou do not need to be told twice. If a CDC violation shows up, you fix it. If a customer asks a tough question about your design, you answer it with specifics, not hand-waving. At Synopsys, you will work on DesignWare IP cores that power everything from automotive systems to enterprise infrastructure. The designs are complex, the standards are real, and what you build will matter.\nWhat You'll Be Doing\nDesign and architect next-generation high-performance RTL for DesignWare IP cores targeting commercial, enterprise, and automotive applications\nTranslate IEEE 802.3 specifications and customer requirements into detailed micro-architecture documents and synthesizable Verilog or SystemVerilog RTL\nOwn RTL implementation end to end, including coding, synthesis with Fusion Compiler or similar tools, CDC analysis, formal verification, and timing closure at speeds exceeding 600MHz\nBuild complex datapath architectures such as Reed Solomon FEC encoders and decoders, BCH codes, parallel CRC engines, and MAC SEC blocks with clear area, latency, and throughput trade-offs\nDebug and resolve design issues across lint, CDC, synthesis, and static timing flows using industry-standard tools\nCollaborate with global teams of designers, verification engineers, and customers to refine specifications, resolve technical challenges, and deliver production-quality IP\nMentor and technically lead a small team of designers, reviewing their work and guiding architecture decisions\nThe Impact You Will Have\nYour RTL designs will ship in high-volume products across automotive, enterprise, and commercial markets, directly affecting performance and reliability\nYou will define micro-architectures that set the standard for area efficiency, timing closure, and power consumption in next-generation DesignWare IP\nYour ability to close timing at high frequencies will enable customers to meet aggressive performance targets in their SoCs\nYour architectural decisions will influence how DesignWare IP scales across protocol generations, from Ethernet to PCIe to MIPI\nYour mentorship will elevate the technical capabilities of the design team and improve the quality of deliverables across the board\nYour collaboration with customers will ensure that Synopsys IP meets real-world requirements, not just spec checkboxes\nYour contributions to design flows, synthesis methodologies, and quality processes will strengthen the entire IP development pipeline\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics, or VLSI with 5 to 10 years of hands-on RTL design experience\nProven track record designing datapath blocks such as Reed Solomon FEC, BCH codes, parallel CRC, or MAC SEC engines with demonstrable trade-offs in area, latency, and throughput\nDeep experience with synthesizable Verilog or SystemVerilog RTL coding for ASIC designs, including lint, CDC, synthesis, and formal verification flows\nHands-on experience closing timing on designs running at 600MHz or higher, ideally using physical-aware synthesis tools like Fusion Compiler\nStrong knowledge of at least one industry protocol: Ethernet, DDR, PCIe, USB, MIPI, or AMBA (AXI, AHB)\nExperience with control path designs such as asynchronous FIFOs, DMA architectures, and SPRAM or DPRAM interfaces\nFamiliarity with Perforce or similar version control systems and scripting in Perl or shell is a plus\nWho You Are\nYou can take a 200-page IEEE specification, extract the critical design requirements, and turn it into a working micro-architecture without needing someone to hold your hand\nYou do not just write RTL, you think about what happens when it hits synthesis, when it goes through CDC analysis, and when it runs at 800MHz in a customer's SoC\nYou can sit in a design review, explain a complex datapath trade-off in two minutes, and answer tough questions without getting defensive\nYou have mentored other engineers before, whether formally or informally, and you know how to give feedback that actually helps someone improve\nYou are comfortable working across time zones with teams in the US, Europe, and Asia, and you do not let communication gaps slow down progress\nYou take ownership, if something breaks in your design, you do not wait for someone else to notice, you fix it\nThe Team You'll Be Part Of\nYou will join the DesignWare IP Design R&D team in Bangalore, part of Synopsys IP Group. This is a global team of expert engineers working on state-of-the-art synthesizable IP cores that ship in high-volume commercial, enterprise, and automotive products. You will collaborate with RTL designers, verification engineers, and architects across multiple sites worldwide. This is a technical individual contributor role with opportunities to lead design efforts and mentor other engineers. The team works on cutting-edge IP using the latest HDL and design flows, and you will have direct exposure to customer requirements and industry-leading design methodologies.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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