{"id":1311366,"url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-3","title":"ASIC Digital Design, Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":89,"ghost_share":0.034,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":11,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":39000,"max_usd":79000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":459},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"closed","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-07T14:55:29Z","board_verified":false,"closed_at":"2026-10-07T14:55:29Z","days_open":10,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":10},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the trenches of digital design where the difference between RTL that synthesizes cleanly and RTL that becomes someone else's nightmare is a decision you made on Tuesday. You know that writing Verilog is the easy part. The hard part is writing Verilog that closes timing, passes CDC without waivers, and does not make the implementation team want to rewrite your entire block.\nYou think about synthesis while you write RTL. Timing arcs are not abstract concepts, they are the reason you structured that state machine the way you did. When a design review surfaces a potential CDC issue, you are already three steps ahead, sketching the synchronizer and thinking through the corner cases.At Synopsys, you will work on real IP that ships in real products.\nWhat You'll Be Doing\nDesign and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog.\n Refine micro-architecture with focus on synthesizability, timing, testability, area, and power tradeoffs.\nDrive synthesis and front-end implementation activities.\nSupport CDC/RDC/Lint signoff readiness and collaborate on design-quality closure.\nWork with implementation teams on STA fundamentals, timing constraints, and timing arc understanding.\nCollaborate with verification teams on functional debug, test planning, assertions, and coverage.\nSupport debug and issue resolution using Verdi or similar debug tools.\nParticipate in design reviews and help resolve integration and interoperability issues across product lines.\nDevelop automation scripts for design, debug, reporting, and productivity.\nThe Impact You Will Have\nYour RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide\nYou will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs\nYour collaboration will catch issues earlier, reducing costly respins and late-stage fixes\nThe automation you build will improve design productivity across multiple product lines\nYour attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk\nWhat You'll Need\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n4+ years of experience in digital design and/or RTL development.\nPractical knowledge of Verilog/SystemVerilog.\nPractical understanding of the ASIC design flow.\nStrong background in synthesis, front-end implementation, and design-for-closure methodology.\nPractical understanding of STA, timing constraints, and timing arcs.\nExperience with CDC/RDC/Lint concepts and signoff-ready design practices.\nAbility to collaborate effectively with verification, implementation, and validation teams.\nScripting experience in Python, Tcl, Perl, or Shell.\nStrong communication and cross-team collaboration skills.\nNice to Have\nExperience with PCIe, USB, or UCIe-based designs.\nExperience with Verdi or other waveform/debug tools.\nExposure to UVM or formal verification concepts.\nExperience with interface IP or protocol bring-up.\nPrior experience in a global product engineering environment.\nWho You Are\nYou can sit in a design review, absorb feedback from three different teams, and walk out with a clear plan\nYou do not wait for perfect specs, you work with what you have and ask the right questions\nYou can explain a timing closure issue to an implementation engineer and a CDC violation to a verification engineer in the same afternoon\nYou are comfortable debugging a waveform in Verdi to find the one-cycle glitch that breaks the protocol handshake\nYou write scripts because running the same check manually 47 times is not how you want to spend your week\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":4869,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"},{"event":"close","at":"2026-10-07T14:55:29Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-3","json_url":"https://alion.io/job/synopsys-asic-digital-design-staff-engineer-3.json","meta":{"generated_at":"2026-10-12T14:13:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22453,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-digital-design-staff-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-digital-design-staff-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-digital-design-staff-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-digital-design-staff-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-digital-design-staff-engineer-3"}]}