{"id":3892133,"url":"https://alion.io/job/synopsys-asic-physical-design-principal-engineer-19305","title":"ASIC Physical Design, Principal Engineer - 19305","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-11-06T21:49:56Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-11T23:17:39Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade taking SerDes and high-speed interface IP from RTL to silicon, and you know that the hardest problems are not the ones in the datasheet. They are the ones that show up at 16nm when your timing closure strategy collides with a power domain you did not account for, or when a customer integration uncovers an assumption you made six months ago that no longer holds. You are the engineer who catches those problems early, not because you are paranoid, but because you have seen what happens when they slip through.\nYou think in terms of flows, not just tasks. You know how to write the constraints that actually work, not just pass checks. You have debugged analog-digital interfaces enough times to respect the boundary and know when to pull in the right person instead of guessing. You can talk architecture with front-end teams, timing with CAD, and integration pain points with a customer who is three weeks from tapeout and needs a real answer, not a workaround.\nAt Synopsys, you will work on 112G and 224G PAM4/6 SerDes IP at nodes where every decision about placement, clocking, and power matters. The team is technical, the problems are real, and what you build will ship in products that move data at scale.\nWhat You'll Be Doing\nOwn physical integration for advanced SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below\nDrive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes, working closely with front-end, analog, and CAD teams to resolve integration challenges\nDevelop and validate timing constraints, clock architectures, and low-power design techniques that meet customer PPA targets and enable first-pass silicon success\nLead customer engagements on physical integration topics, including SOC-level integration planning, constraint delivery, and tapeout support\nBuild and improve design methodologies, automation scripts (Perl, Tcl, Python), and flows that reduce customer effort and improve delivery predictability\nDebug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams\nMentor engineers across the team on physical design best practices, timing closure strategies, and advanced node challenges\nThe Impact You Will Have\nYour physical integration work will enable high-speed SerDes IP to meet aggressive PPA targets in customer SoCs across data center, AI, and networking applications\nYou will reduce customer integration effort and risk by delivering robust constraints, proven flows, and clear guidance that accelerates their tapeout schedules\nYour methodology improvements and automation will make the entire team faster and more consistent, reducing rework and late-stage surprises\nYou will help shape the technical direction of future SerDes products by identifying architectural and flow improvements based on real tapeout learnings\nYour customer interactions will surface integration challenges early, allowing the team to address them in IP rather than forcing workarounds downstream\nYou will build technical depth across the team by sharing what you have learned from advanced node tapeouts and complex mixed-signal integration\nYour work will directly contribute to the success of Synopsys SerDes IP in the most demanding, highest-performance applications in the industry\nWhat You'll Need\nMSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, with recent contributions to project tapeouts\nDeep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff\nProven experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges\nStrong understanding of timing constraint development, clock architecture, and design techniques required to meet power and area targets\nExperience leading technical initiatives or projects, with a track record of driving decisions and delivering results on schedule\nSolid understanding of digital and mixed-signal verification flows, SOC integration challenges, and analog-digital interface considerations\nStrong scripting and automation skills in Perl, Tcl, or Python, with a methodology-driven approach to design and CAD flows\nWho You Are\nYou can walk into a customer meeting three weeks before tapeout, understand their integration issue in fifteen minutes, and give them a path forward that actually works\nYou make decisions with incomplete information because you know waiting for perfect clarity is not an option, and you are comfortable owning the call\nYou know when a timing problem is a constraint problem, a floorplan problem, or an architecture problem, and you do not waste time solving the wrong one\nYou push back when a plan does not make sense, whether it is a schedule, a methodology, or a customer request that will create more problems than it solves\nYou can explain a complex physical design tradeoff to an analog engineer, a front-end architect, and a customer program manager, and have all three understand what matters to them\nYou are comfortable with international travel when customer engagements or team collaboration require it\nThe Team You'll Be Part Of\nYou will be part of the Enterprise SerDes IP team, a group responsible for delivering high-speed interface IP across 56G, 112G, and 224G standards. The team works closely with front-end design, analog engineering, CAD, and product teams, as well as directly with customers on integration and tapeout support. Your work will involve collaboration across multiple internal functional groups and regular interaction with both internal and external customers.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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