{"id":1515539,"url":"https://alion.io/job/synopsys-asic-physical-design-sr-engineer-18156","title":"ASIC Physical Design, Sr Engineer - 18156","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":42000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Validator","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-09-30T09:23:48Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-14T10:33:58Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years turning RTL into silicon that actually works, not just passes checks, but ships, performs, and comes back from the fab without surprises. You know that a floorplan decision made in week two will either save or cost you three weeks at tape-out, and you are the kind of engineer who sees that trade-off clearly and makes the call with confidence. You have lived through enough timing closures to know when a violation is real and when it is noise, and you do not panic when the sign-off checklist grows to 47 items two days before delivery.\nScripting is not a side task for you, it is how you scale yourself. You write Tcl and Python that other engineers can actually read and use, because you have seen what happens when flows are held together by one person's undocumented magic. You do not wait for perfect documentation from the foundry. You read what exists, ask the right questions, and build a methodology that works within the constraints you have. When IR-drop blows up or a clock tree will not converge, you dig in, find the root cause, and fix it in a way that does not break three other things downstream.\nWhat You'll Be Doing\nOwn the full RTL-to-GDSII physical implementation flow for memory test-chip blocks and top-level designs, driving synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off closure\nDevelop and maintain Back-End implementation and sign-off flows including PnR, STA, PV, IR/EM analysis, and extraction methodologies\nReview and implement foundry sign-off requirements and tape-out checklists, ensuring manufacturing compliance and first-pass silicon success\nExecute timing analysis and closure across multiple PVT corners, optimizing for power, performance, and area\nDrive physical and electrical verification using Synopsys IC Validator, resolving DRC, LVS, ERC, antenna, EM, IR-drop, and signal integrity issues\nCollaborate with Foundry, CAD, Front-End, DFT, STA, and Design teams to resolve implementation challenges and hit project milestones\nBuild automation frameworks and scripts in Python, Tcl, and Perl that improve design productivity and flow efficiency\nThe Impact You Will Have\nEnable successful first-pass silicon for memory test-chip designs by delivering clean, manufacturable GDSII with complete sign-off collateral\nReduce design cycle time through robust, repeatable Back-End flows that scale across multiple projects and process nodes\nEliminate late-stage surprises by catching timing, power, and physical issues early and building methodologies that prevent recurrence\nStrengthen foundry partnerships by implementing sign-off requirements correctly and providing feedback that improves design enablement\nAccelerate team productivity by delivering automation that removes manual bottlenecks and makes complex tasks repeatable\nContribute to Synopsys IP competitiveness by ensuring memory designs meet aggressive performance and power targets on advanced nodes\nElevate team capability by sharing knowledge, documenting best practices, and building flows others can learn from and extend\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline\n5+ years of hands-on ASIC physical design experience with proven silicon tape-outs, ideally on advanced process nodes\nDeep expertise across the full RTL-to-GDSII implementation flow including synthesis, floorplanning, power planning, placement, CTS, routing, and sign-off\nStrong proficiency with Synopsys tools including Fusion Compiler or ICC2, PrimeTime, StarRC, and IC Validator\nSolid scripting and automation skills in Tcl, Python, and Perl with a track record of building flows that improve team efficiency\nExperience setting up and maintaining Back-End design and sign-off methodologies including PnR, STA, PV, extraction, and IR/EM analysis\nAbility to interpret and implement foundry sign-off requirements and tape-out checklists to ensure manufacturing readiness\nWho You Are\nYou can look at a floorplan and immediately see the congestion, power, or timing problems that will surface later, and you address them before they become crises\nWhen a sign-off violation appears, you dig into the data, trace it to root cause, and fix it in a way that makes sense for the design and the flow\nYou write scripts and build flows with the next engineer in mind, clear variable names, comments that explain why, and structure that someone else can extend\nYou communicate clearly across disciplines, translating technical issues for front-end designers or CAD engineers without losing the thread\nYou stay calm under pressure, especially in the final weeks before tape-out, and you help the team stay focused on what actually matters\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5921,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-30T09:23:48Z"}],"visa":[],"liveness":{"score":40,"band":"fade","label":"Fading","p_open":1,"p_active":0.735,"p_room":0.55,"age_days":13,"expected_fill_days":12,"reasons":["conf:0","velocity","win:tail","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-physical-design-sr-engineer-18156","json_url":"https://alion.io/job/synopsys-asic-physical-design-sr-engineer-18156.json","meta":{"generated_at":"2026-10-14T11:58:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14471,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-physical-design-sr-engineer-18156"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-physical-design-sr-engineer-18156"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-physical-design-sr-engineer-18156"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-physical-design-sr-engineer-18156\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-physical-design-sr-engineer-18156"}]}