{"id":695422,"url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer-18332","title":"ASIC Physical Design, Sr Staff Engineer 18332","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":48000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-09-11T01:53:52Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-23T09:43:04Z","board_verified":true,"closed_at":null,"days_open":42,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":42},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years in the trenches of physical design, taking complex IP from RTL to GDS, and you know that the difference between a design that tapes out on schedule and one that slips is usually a decision you made during floorplanning or a timing path you caught in week two instead of week ten. You have seen enough 5nm and below tapeouts to know where the landmines are buried, and you are the engineer who spots them before they blow up the schedule.\nYou do not wait for perfect specs. When the RTL is still settling and the foundry deck has a known issue, you start floorplanning anyway because you know what matters and what can wait. You have strong opinions about ICC2 strategies, about when to push timing versus area, about which corners actually matter for signoff. You are comfortable defending those opinions in a room full of architects and verification leads, and you are equally comfortable changing your mind when the data says you should.\nAt Synopsys, you will be working on UCIe PHYs and testchips that define how chips connect in the next generation of systems. The designs are real, the nodes are leading edge, and the team expects you to lead, not just execute.\nWhat You'll Be Doing\nOwn physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes\nDrive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects\nWork directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule\nLead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers\nPilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team\nMentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively\nInterface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions\nThe Impact You Will Have\nDeliver production-quality UCIe PHY designs that enable next-generation chip-to-chip connectivity for Synopsys customers building AI accelerators, data center processors, and high-performance compute systems\nImprove design cycle time and PPA outcomes by driving tooling and methodology improvements across the physical design flow that the entire IP team will adopt\nHandle multiple concurrent tapeouts in leading-edge technologies, ensuring Synopsys meets customer commitments and maintains its reputation for on-time silicon delivery\nStrengthen customer confidence in Synopsys IP through high-quality signoff, responsive technical engagement during integration, and designs that actually work in silicon\nInfluence product roadmap decisions by surfacing design insights and PPA tradeoffs that matter to end customers during architecture and planning phases\nContribute to how Synopsys approaches physical design for 3nm and beyond by piloting new flows, feeding lessons learned back into the methodology team, and shaping best practices\nEnable faster time-to-market for customers by delivering UCIe IP that integrates cleanly, meets timing out of the box, and requires minimal rework during SoC integration\nWhat You'll Need\n7+ years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification\nMultiple tapeouts and signoffs in 5nm or more advanced process nodes, you have taken designs all the way to GDS and dealt with the messiness that comes with it\nProficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, you know the commands, the flow, and the workarounds\nProven track record working on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff\nStrong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale\nExperience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues\nExposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, we care more about your physical design depth and ability to learn quickly\nWho You Are\nYou can walk into a timing review with 500 failing paths and know within ten minutes which ones actually matter and which ones are tool artifacts or false paths\nYou are comfortable making tradeoff calls under pressure, like choosing to upsize a cell and take the area hit because you know the timing margin is real and the schedule cannot slip\nYou do not need someone to tell you what to do next, when floorplan is done, you move to placement, when placement converges, you start clock tree, and you flag blockers before they become emergencies\nYou can explain a complex physical design issue to an architect or a customer engineer in two sentences without losing the technical nuance that matters\nYou have mentored junior engineers before, not in a formal program, but because someone asked you a question and you took the time to show them the right way instead of just giving them the answer\nYou are organized enough to manage three tapeouts at different stages without dropping details, and you know how to keep stakeholders informed without over-communicating\nThe Team You'll Be Part Of\nYou will be part of an engineering team dedicated to implementing UCIe PHY and testchips. The team focuses on the full physical design flow, encompassing synthesis, physical design, verification, design for test, and ATPG. You will collaborate with both internal and external design teams, contributing to complex projects and driving technological innovation in advanced connectivity IP.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":7068,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-11T01:53:52Z"},{"event":"close","at":"2026-09-14T10:55:12Z"},{"event":"reopen","at":"2026-09-14T13:55:24Z"}],"visa":[],"liveness":{"score":22,"band":"cold","label":"Long shot","p_open":1,"p_active":0.621,"p_room":0.35,"age_days":42,"expected_fill_days":15,"reasons":["conf:1","velocity","win:tail","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer-18332","json_url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer-18332.json","meta":{"generated_at":"2026-10-23T12:20:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18795,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer-18332"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer-18332"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer-18332"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-physical-design-sr-staff-engineer-18332\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer-18332"}]}