{"id":1652019,"url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer","title":"ASIC Physical Design, Sr Staff Engineer","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys SpyGlass","optional":false}],"status":"live","first_seen_at":"2026-10-02T00:31:24Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-13T13:16:05Z","board_verified":true,"closed_at":null,"days_open":11,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":11},"description":"Job Description and Requirements\nJob Description and Requirements\nWe Are:\n At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to new tools and technologies. You value open communication, inclusivity, and knowledge sharing, and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.\nWhat You'll Be Doing:\n\nLead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.\nWork closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.\nAnalyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.\nPerform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.\nCollaborate with cross-functional teams to define and implement best practices for DFT methodologies and flows.\nContribute to the continuous improvement of automation scripts and design flows to boost efficiency and reduce turnaround time.\nThe Impact You Will Have:\n\nEnhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.\nDrive innovation in DFT flows, setting new standards for quality and efficiency within the organization.\nEnable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.\nRepresent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.\nEmpower cross-functional teams by sharing expertise, fostering a culture of continuous improvement and collaboration.\nContribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.\nWhat You'll Need:\n\nExtensive hands-on experience with 3-10yrs in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.\nProficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.\nStrong understanding of digital logic design, RTL coding, and verification principles.\nDemonstrated ability to debug and resolve DFT-related issues across multiple project phases.\nSolid scripting skills (e.g., TCL, Perl, Python) to automate design and test flows.\nWho You Are:\n\nCollaborative team player who communicates effectively across functions and cultures.\nProactive problem solver, comfortable with ambiguity and rapid change.\nDetail-oriented and highly organized, with a commitment to delivering high-quality results.\nInclusive and open-minded, eager to share knowledge and mentor others.\nSelf-motivated and driven by curiosity, with a continuous learning mindset.\nThe Team You'll Be A Part Of:\n You will join a dynamic and innovative DFT team within Synopsys' Engineering organization in Bangalore. The team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.\nRewards and Benefits:\n We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5289,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-02T00:31:24Z"}],"visa":[],"liveness":{"score":56,"band":"ok","label":"Likely open","p_open":1,"p_active":0.748,"p_room":0.75,"age_days":11,"expected_fill_days":12,"reasons":["conf:2","velocity","win:late","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer","json_url":"https://alion.io/job/synopsys-asic-physical-design-sr-staff-engineer.json","meta":{"generated_at":"2026-10-13T16:06:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24509,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-asic-physical-design-sr-staff-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-asic-physical-design-sr-staff-engineer"}]}