ATE Test Engineer, Sr Staff Engineer - 18756

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in electronics labs. You know that silicon does not always behave like the simulation promised, and you are the person who figures out why, whether it is a PLL locking issue, a signal/power integrity problem on the board, or a test program that is measuring the wrong edge.

You are comfortable moving between ATE programming on Teradyne or Advantest platforms and oscilloscope-based debug without losing sight of what you are validating. When a DDR timing fails, you do not just flag it,you trace it back to whether it is silicon behavior, firmware configuration, or test fixture noise. You have debugged enough mixed-signal systems to know when a jitter spike is real and when it is an artifact of your measurement setup.

At Synopsys, you will work on memory interface IP that powers real customer products, and your validation work will determine whether that IP ships on time and works in the field.

What You'll Be Doing

• Develop and execute ATE test programs on platforms like Introspect, Teradyne, Advantest, or Credence for memory interface IP including DDR, LPDDR, and HBM
• Perform electrical characterization using oscilloscopes, BERTs, and network analyzers to capture time-domain signals, eye diagrams, and jitter analysis on production silicon
• Debug complex mixed-signal systems including PLLs, DLLs, DACs, and state machines to isolate failures across silicon, firmware, board, and test setup
• Validate IP against JEDEC specifications and automotive qualification standards including HTOL, ELFR, and reliability testing protocols
• Generate technical documentation and validation reports that translate silicon behavior into actionable recommendations for design, firmware, and customer teams
• Collaborate with design and firmware teams during silicon bring-up to identify and resolve issues before production release
• Mentor junior validation engineers through characterization projects, test program development, and lab equipment usage

The Impact You Will Have

• Your validation work will determine whether Synopsys memory IP meets timing, signal integrity, and reliability requirements before customer deployment
• You will catch silicon issues early in the validation cycle, reducing costly re-spins and accelerating time to market for new IP releases
• Your ATE programs will become the production test foundation for high-volume manufacturing, directly affecting yield and quality
• Your characterization data will inform design decisions for next-generation memory interface IP
• Your mentorship will build validation capability in the Nepean lab, enabling the team to scale alongside the IP portfolio
• Your documentation will serve as the technical record that supports customer engagements, qualification processes, and internal design reviews
• Your ability to isolate root cause across disciplines will prevent validation bottlenecks and keep silicon programs on schedule

What You'll Need

• Bachelor's or Master’s degree in Electrical Engineeringor equivalent technical field
• 8+ years of hands-on experience in silicon validation, ATE programming, or mixed-signal test engineering
• Proven experience programming ATE platforms such as Teradyne, LTX, Advantest, Credence, or Introspect
• Proven experience debugging and bringing up new benchtop test equipment (clock/function generators, power supplies, part pickers, etc.) for IO characterization (i.e. driver/receiver, BERT, impedance, clock jitter, compliance test, semiconductor reliability, WAT, etc.)
• Deep working knowledge of DDR, LPDDR, and HBM protocols and JEDEC specifications
• Strong analog and mixed-signal circuit knowledge with the ability to analyze verification and simulation waveforms
• Expertise using oscilloscopes, BERTs, network analyzers, and other advanced lab equipment for electrical characterization
• Expertise in reading VB code
• Experience with jitter analysis, timing validation, pulse-width measurements, and reliability testing including HTOL and ELFR is a strong plus
• Familiarity with automotive qualification standards is a strong plus

Who You Are

• You drive complex technical problems independently across multiple disciplines without waiting for direction
• You diagnose whether a failure is silicon, firmware, board, or test setup and make the call quickly
• You translate technical findings into clear recommendations that design, firmware, and customer teams can act on
• You mentor junior engineers through their first characterization projects without taking over the work
• You push back when validation coverage is thin or root cause stops at correlation instead of causation

The Team You'll Be Part Of

You will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].