{"id":1311357,"url":"https://alion.io/job/synopsys-ate-test-engineer-sr-staff-engineer-18756","title":"ATE Test Engineer, Sr Staff Engineer - 18756","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":99,"ghost_share":0.03,"stale_share":0,"repost_share":0.162,"time_to_fill_p50_days":7,"computed_at":"2026-09-27T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":95000,"max_usd":216000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":82},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"BERT","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T19:50:00Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in electronics labs. You know that silicon does not always behave like the simulation promised, and you are the person who figures out why, whether it is a PLL locking issue, a signal/power integrity problem on the board, or a test program that is measuring the wrong edge.\nYou are comfortable moving between ATE programming on Teradyne or Advantest platforms and oscilloscope-based debug without losing sight of what you are validating. When a DDR timing fails, you do not just flag it,you trace it back to whether it is silicon behavior, firmware configuration, or test fixture noise. You have debugged enough mixed-signal systems to know when a jitter spike is real and when it is an artifact of your measurement setup.\nAt Synopsys, you will work on memory interface IP that powers real customer products, and your validation work will determine whether that IP ships on time and works in the field.\nWhat You'll Be Doing\nDevelop and execute ATE test programs on platforms like Introspect, Teradyne, Advantest, or Credence for memory interface IP including DDR, LPDDR, and HBM\nPerform electrical characterization using oscilloscopes, BERTs, and network analyzers to capture time-domain signals, eye diagrams, and jitter analysis on production silicon\nDebug complex mixed-signal systems including PLLs, DLLs, DACs, and state machines to isolate failures across silicon, firmware, board, and test setup\nValidate IP against JEDEC specifications and automotive qualification standards including HTOL, ELFR, and reliability testing protocols\nGenerate technical documentation and validation reports that translate silicon behavior into actionable recommendations for design, firmware, and customer teams\nCollaborate with design and firmware teams during silicon bring-up to identify and resolve issues before production release\nMentor junior validation engineers through characterization projects, test program development, and lab equipment usage\nThe Impact You Will Have\nYour validation work will determine whether Synopsys memory IP meets timing, signal integrity, and reliability requirements before customer deployment\nYou will catch silicon issues early in the validation cycle, reducing costly re-spins and accelerating time to market for new IP releases\nYour ATE programs will become the production test foundation for high-volume manufacturing, directly affecting yield and quality\nYour characterization data will inform design decisions for next-generation memory interface IP\nYour mentorship will build validation capability in the Nepean lab, enabling the team to scale alongside the IP portfolio\nYour documentation will serve as the technical record that supports customer engagements, qualification processes, and internal design reviews\nYour ability to isolate root cause across disciplines will prevent validation bottlenecks and keep silicon programs on schedule\nWhat You'll Need\nBachelor's or Master’s degree in Electrical Engineeringor equivalent technical field\n8+ years of hands-on experience in silicon validation, ATE programming, or mixed-signal test engineering\nProven experience programming ATE platforms such as Teradyne, LTX, Advantest, Credence, or Introspect\nProven experience debugging and bringing up new benchtop test equipment (clock/function generators, power supplies, part pickers, etc.) for IO characterization (i.e. driver/receiver, BERT, impedance, clock jitter, compliance test, semiconductor reliability, WAT, etc.) \nDeep working knowledge of DDR, LPDDR, and HBM protocols and JEDEC specifications\nStrong analog and mixed-signal circuit knowledge with the ability to analyze verification and simulation waveforms\nExpertise using oscilloscopes, BERTs, network analyzers, and other advanced lab equipment for electrical characterization\nExpertise in reading VB code\nExperience with jitter analysis, timing validation, pulse-width measurements, and reliability testing including HTOL and ELFR is a strong plus\nFamiliarity with automotive qualification standards is a strong plus\nWho You Are\nYou drive complex technical problems independently across multiple disciplines without waiting for direction\nYou diagnose whether a failure is silicon, firmware, board, or test setup and make the call quickly\nYou translate technical findings into clear recommendations that design, firmware, and customer teams can act on\nYou mentor junior engineers through their first characterization projects without taking over the work\nYou push back when validation coverage is thin or root cause stops at correlation instead of causation\nThe Team You'll Be Part Of\nYou will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":6130,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":7,"reasons":["conf:9","velocity","win:early","comp:brand"],"computed_at":"2026-09-27T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-ate-test-engineer-sr-staff-engineer-18756","json_url":"https://alion.io/job/synopsys-ate-test-engineer-sr-staff-engineer-18756.json","meta":{"generated_at":"2026-09-28T03:11:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2004,"day_limit":5000,"remaining_today":2996,"minute_limit":60,"resets_at":"2026-09-29T00:00:00Z"}}}