{"id":2357705,"url":"https://alion.io/job/synopsys-design-verification-staff-engineer-19165","title":"Design Verification Staff Engineer - 19165","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":false}],"status":"live","first_seen_at":"2026-10-12T15:04:19Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-13T05:48:48Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAlternate Job TitlesStaff Verification Applications Engineer\nSenior Technical Applications Engineer, RTL Verification\nStaff Field Applications Engineer, Design Verification\nTechnical Lead, Verification Solutions\nStaff Applications Engineer, Timing and Verification\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade in the trenches of digital design, where timing exceptions are not theoretical exercises but the difference between a chip that tapes out and one that doesn't. You know what it looks like when a customer's constraint deck has 3,000 false paths and half of them are wrong, and you know how to walk them back from that edge without making them feel like they've been doing it wrong for years.\nYou are comfortable sitting with a design team in Hsinchu on Tuesday debugging why their CDC violations won't converge, then jumping on a call with R&D in Mountain View on Wednesday to explain exactly what the tool needs to do differently. You translate between what the tool can do and what the customer actually needs, and you do it without losing either side.\nMethodology deployment is your craft. You have built flows that teams actually use, not ones that look good in a slide deck. You script in Tcl and Python because you have to, not because you love it, and you have debugged enough PrimeTime correlation issues to know that the problem is usually three layers deeper than where it first appears. At Synopsys, you will work with Taiwan's most strategic semiconductor accounts on verification and timing solutions that determine whether their next-generation SoCs actually work.\nWhat You'll Be Doing\nLead full-cycle deployments of Timing Constraints Management (TCM), VC SpyGlass, and VCS across strategic accounts, from evaluation through production adoption and methodology integration\nDebug complex timing constraint issues including false path validation, multi-cycle path analysis, clock-domain crossing verification, and STA-to-simulation correlation problems in real customer designs\nDrive pilot projects that prove out constraint verification, RTL quality checking, and simulation-based timing validation flows in advanced-node SoC environments\nBuild automation scripts and reusable deployment methodologies in Tcl, Python, and Perl that improve customer productivity and reduce time to signoff\nDeliver technical workshops and hands-on training on TCM constraint management, VC SpyGlass lint/CDC/RDC flows, and VCS simulation debug techniques\nCollaborate directly with R&D teams to escalate critical customer issues, validate new features, and shape product roadmaps based on what you see in the field\nPartner with sales and product management to identify technical expansion opportunities within accounts and translate customer pain points into business growth\nThe Impact You Will Have\nEnable Taiwan semiconductor leaders to close timing on complex SoCs faster by deploying constraint verification methodologies that catch errors before they reach signoff\nReduce customer debug cycles by building simulation and formal flows that correlate cleanly with static timing analysis, eliminating weeks of back-and-forth\nDrive adoption of VC SpyGlass across RTL verification teams, improving design quality and reducing CDC/RDC violations that would otherwise escape to silicon\nShape how Synopsys verification tools evolve by feeding real customer use cases and methodology gaps directly back to product development\nAccelerate time-to-production for strategic accounts by creating reusable deployment frameworks that scale across multiple design teams and projects\nBuild long-term technical relationships with customer architects and methodology leads, becoming the trusted advisor they call when a critical project is at risk\nExpand Synopsys footprint in key accounts by proving technical value in one domain and opening doors to adjacent tool adoption\nWhat You'll Need\nMS in Electrical Engineering, Computer Engineering, or equivalent technical discipline\n10+ years of hands-on experience in digital design implementation, static timing analysis, RTL verification, or signoff methodologies in a production environment\nDeep working knowledge of SDC constraints, timing exceptions, false path and multi-cycle path analysis, clock-domain crossing, and timing closure flows\nProven experience debugging timing correlation issues between simulation-based validation and STA tools like PrimeTime or Tempus\nStrong technical background in lint, CDC, RDC, and structural verification methodologies, ideally with tools like VC SpyGlass or equivalent\nProficiency scripting in Tcl, Python, Perl, or shell for automation, flow development, and customer-specific methodology customization\nExperience supporting advanced-node SoC or ASIC designs is a strong plus, familiarity with enterprise-scale verification deployment across multiple teams is valuable\nWho You Are\nYou can walk into a war room where a customer's timing closure is stuck and within an hour identify whether the problem is a constraint issue, a tool setup issue, or a fundamental methodology gap\nYou explain complex tradeoffs to customer architects in two sentences without losing the nuance, and you know when to simplify and when to go deep\nYou manage multiple customer engagements simultaneously without dropping threads, keeping internal teams aligned and customers confident that their issues are moving forward\nYou push back when a deployment plan is missing critical steps or when a customer is headed toward a methodology dead-end, and you do it in a way that builds trust rather than friction\nYou are comfortable with ambiguity, working from incomplete design data, evolving requirements, and customer environments where the documentation is six months out of date\nYou treat customer success as your success, not because it's in a mission statement but because you know that a clean tapeout using your methodology is what actually matters\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":7071,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-12T15:04:19Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":12,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-design-verification-staff-engineer-19165","json_url":"https://alion.io/job/synopsys-design-verification-staff-engineer-19165.json","meta":{"generated_at":"2026-10-13T09:05:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13661,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-design-verification-staff-engineer-19165"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-design-verification-staff-engineer-19165"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-design-verification-staff-engineer-19165"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-design-verification-staff-engineer-19165\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-design-verification-staff-engineer-19165"}]}