{"id":3133560,"url":"https://alion.io/job/synopsys-eda-flow-and-logic-synthesis-engineer-19292","title":"EDA flow and Logic Synthesis Engineer---19292","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":73,"ghost_share":0.055,"stale_share":0,"repost_share":0.205,"time_to_fill_p50_days":15,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Wuhan, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":8444},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"TCL Scripting","optional":false},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-10-23T04:49:10Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-30T16:38:03Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence - from self-driving cars to learning machines - and we lead in chip design, verification, and IP integration that power high-performance silicon and software.\nWithin our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation. We build the flows, automation, and quality checks that synthesize, verify, package, and release complex soft IP at scale - and we hand physical-design teams inputs that are clean, constrained, and implementation-ready.\nYou Are:\nA motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results. You partner naturally with RTL designers to understand design intent, turn their outputs into physical-design-ready inputs, and collaborate across verification, DFT, physical design, methodology, and tooling teams. You communicate clearly, take ownership, and let data guide your decisions.\nWhat You’ll Be Doing:\nDevelop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.\nConvert RTL outputs into clean, constrained, implementation-ready inputs for physical design.\nBuild and maintain Tcl-based automation, dashboards, and project infrastructure - and apply AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts).\nDebug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.\nImprove documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.\nThe Impact You Will Have:\nHigher-quality RTL-to-physical-design handoffs and lower implementation risk.\nFaster, more scalable execution through stronger automation and AI-enabled analysis.\nSynthesis, DFT, static, formal, and power issues caught earlier in the cycle.\nTighter collaboration across the RTL-to-implementation chain.\nRobust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.\nWhat You’ll Need(Core):\nWorking knowledge of ASIC design, verification, and mid-end development flows, typically gained through 5+ years of relevant experience or equivalent project work.\nHands-on synthesis experience, with the ability to analyze and resolve synthesis issues.\nStrong Tcl scripting skills and a practical, automation-first mindset.\nFamiliarity with at least two of: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis - and willingness to grow across the rest.\nAbility to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.\nStrong analytical, problem-solving, communication, and documentation skills.\nBS/MS in Electrical/Computer Engineering or equivalent experience.\nNice to have :\nExperience across the full mid-end set: DFT, SpyGlass, Formality, and power analysis.\nIP development methodologies, IP packaging, or reusable IP delivery / release collateral.\nHands-on with Synopsys tools such as Fusion Compiler and VC SpyGlass.\nWho You Are:\nProactive, curious, and adaptable.\nCollaborative and ethical.\nFlow-oriented, AI-aware, and quality focused.\nResilient and results oriented.\nThe Team You’ll Be A Part Of:\nYou’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about salary and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":4437,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-23T04:49:10Z"}],"visa":[],"liveness":{"score":80,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.888,"p_room":0.9,"age_days":7,"expected_fill_days":15,"reasons":["conf:2","velocity","win:mid","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-eda-flow-and-logic-synthesis-engineer-19292","json_url":"https://alion.io/job/synopsys-eda-flow-and-logic-synthesis-engineer-19292.json","meta":{"generated_at":"2026-10-30T17:47:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6511,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-eda-flow-and-logic-synthesis-engineer-19292"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-eda-flow-and-logic-synthesis-engineer-19292"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-eda-flow-and-logic-synthesis-engineer-19292"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-eda-flow-and-logic-synthesis-engineer-19292\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-eda-flow-and-logic-synthesis-engineer-19292"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3133560}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3133560},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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