{"id":1311349,"url":"https://alion.io/job/synopsys-embedded-memory-design-manager-17876","title":"Embedded Memory Design Manager- 17876","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":99,"ghost_share":0.03,"stale_share":0,"repost_share":0.162,"time_to_fill_p50_days":7,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Da Nang, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":58000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":375},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T19:50:00Z","board_verified":false,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent a decade in memory design, where the difference between a working SRAM and one that fails at corner cases comes down to understanding transistor-level physics at 5nm. Embedded memory is not just another block, it is what makes or breaks power, performance, and area targets for the entire SoC. You have designed memories that taped out, went into production, and shipped in real products.\nManaging a team does not mean you stopped being an engineer. You still review schematics, catch timing issues in sense amplifiers, and push back when specs ignore real silicon behavior. The hardest part of leading design is keeping five engineers aligned on architecture decisions made two months ago, especially when process technology shifts.\nYou are comfortable arguing with system architects about access time versus leakage tradeoffs, then translating that into concrete tasks for your team. You do not wait for perfect specs. You model it in VerilogA, run the numbers, and move. At Synopsys, you will lead memory design work that ends up in chips powering AI accelerators to automotive systems.\nWhat You'll Be Doing\nLead architecture, circuit design, and physical implementation of embedded memory IP including SRAM, register files, TCAM, and ROM across advanced nodes\nDefine block specifications with system architects, translating customer requirements into concrete design targets\nManage circuit and layout engineers, assign work packages, track progress, and coordinate with project management\nExecute design and layout reviews, create documentation including datasheets and design reports\nModel and simulate memory blocks using VerilogA and SystemVerilog to validate architecture before tapeout\nSupport silicon evaluation, analyze field issues, and drive root cause analysis when designs fail\nDrive continuous improvement in design methodologies and technology evaluation with global teams\nThe Impact You Will Have\nDeliver memory IP meeting aggressive power, performance, and area targets for AI, automotive, mobile, and data center SoCs\nEnable faster customer time-to-market with robust, variation-aware memory solutions that work across process corners\nBuild and mentor engineers who can independently own complex memory design challenges\nInfluence memory architecture direction across Synopsys IP portfolio through technical reviews\nReduce design risk and silicon respins by catching issues early through rigorous modeling and simulation\nExpand Synopsys memory IP capabilities into next-generation process nodes\nStrengthen technical depth of the Da Nang design center through mentorship and process improvement\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering, Computer Science, or equivalent\n10+ years in full embedded memory design flow: architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation\nDeep expertise in SRAM, register file, TCAM, and ROM architectures with advanced custom circuit implementations\nDirect experience designing memory IP in advanced nodes (7nm, 5nm, or beyond) with variation-aware design understanding\nStrong knowledge of digital design, verification methodologies, ASIC design flow, and industry-standard EDA tools\nExperience managing engineering teams including task delegation, performance management, and technical mentorship\nWho You Are\nYou explain complex circuit tradeoffs to project managers in two sentences without losing nuance, then debug layout DRC issues with Layout Managers.\nYou ask the right questions when facing ambiguity rather than waiting for someone else to define the problem\nYou review work with a critical eye but without ego, focusing on making designs better\nYou stay current on process technology trends and new memory architectures because what worked at 28nm does not translate to 5nm\nYou manage competing priorities across multiple projects without dropping threads, escalating early when deadlines are at risk\nThe Team You'll Be Part Of\nYou will join the Silicon IP business unit in Da Nang, part of a global team developing memory compiler IP for SoCs across automotive, mobile, AI, and data center markets. The team collaborates with system architects, physical design engineers, and verification teams across multiple Synopsys sites.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5352,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.859,"p_room":1,"age_days":1,"expected_fill_days":7,"reasons":["conf:33","velocity","win:early","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-embedded-memory-design-manager-17876","json_url":"https://alion.io/job/synopsys-embedded-memory-design-manager-17876.json","meta":{"generated_at":"2026-09-29T04:24:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4156,"day_limit":5000,"remaining_today":844,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}