{"id":1311346,"url":"https://alion.io/job/synopsys-engineering-architecture-sr-staff-engineer-18958","title":"Engineering Architecture, Sr Staff Engineer - 18958","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":89,"ghost_share":0.034,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":11,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Munich, Germany"],"countries":["DE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":106000,"max_usd":218000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-12T23:26:11Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":16},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou bring nearly a decade of experience developing performance models and architectural evaluation methodologies that enable critical design decisions before silicon exists. Your work sits at the convergence of hardware design, software optimization, and system-level analysis, and you have developed a disciplined approach to navigating ambiguity when requirements are still being defined, or stakeholders have not yet aligned on the core technical questions.\nYou are equally capable of writing performance critical C++ models and Python-based automation frameworks for design-space exploration. Your thinking spans multiple abstraction layers: RTL implementation, embedded firmware, application workloads, and system topology. You understand which layer drives the answer for any given architectural question.\nCross-functional collaboration is a strength. You have worked effectively with architecture teams focused on power, performance, and area trade-offs, software teams optimizing for latency and throughput, and verification teams driving coverage metrics.\nAt Synopsys, you will contribute to methodologies and reference architectures for next-generation semiconductor systems. The frameworks you develop will influence how customers evaluate chiplet interconnects, multi-die performance, and SoC scalability.\nWhat You'll Be Doing\nDevelop architecture exploration methodologies for SoC, multi-die, and chiplet-based systems to support early design trade-off decisions \nBuild performance models and virtual prototyping environments using C/C++, Python, and SystemC to characterize next-generation semiconductor architectures \nCreate benchmarks, workloads, and design-space exploration tools that enable scalable evaluation of complex hardware/software systems \nCollaborate with architecture, IP, software, and verification teams across Synopsys to define modeling approaches, validation strategies, and proof-of-concept demonstrations \nDrive technical thought leadership by publishing findings, presenting them at conferences, contributing to standards bodies, and sharing best practices internally and externally \nContribute to reference platforms and technical demonstrations that showcase Synopsys IP, EDA tools, and system-level solutions to customers and partners \nIntegrate AI-assisted development workflows into rapid prototyping, automation, and tooling to accelerate methodology development and technical exploration \nThe Impact You Will Have\nEnable architecture teams to evaluate and optimize multi-die and chiplet-based systems before physical implementation, reducing costly late-stage design changes \nAccelerate time-to-insight for customers by delivering reusable workloads and performance models that become the foundation for their own evaluations \nShape the technical direction of Synopsys IP and platform roadmaps by providing data-driven performance analysis and architectural trade-off studies \nReduce verification and bring-up cycles by delivering validated virtual prototyping environments that software and firmware teams can use before silicon availability \nStrengthen Synopsys customer engagements by contributing to technical demonstrations that prove out real-world use cases \nWhat You'll Need\nMS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field \n8+ years of hands-on experience in system architecture, performance modeling, hardware/software co-design, or semiconductor verification \nStrong proficiency in C/C++ and Python for performance-critical modeling, algorithm development, automation, and tooling \nDeep experience with hardware design and verification, including RTL development, simulation, debug, and performance characterization of complex SoC or multi-die systems \nProven track record of technical communication through publications, conference presentations, patents, or contributions to industry standards and technical communities \nExperience with virtual prototyping, design-space exploration tools, or simulation frameworks for architecture evaluation \nExperience integrating AI-assisted development workflows into rapid prototyping, data analysis, or tool development is a strong plus \nWho You Are\nYou can take a vague architectural question and turn it into a concrete modeling plan with defined assumptions, measurable outputs, and a timeline that actually holds \nYou write code that other engineers can pick up six months later without needing you in the room to explain it \nYou are comfortable presenting technical findings to a room that includes both deep RTL experts and software architects who have never touched Verilog, and you calibrate your message accordingly \nYou treat proof-of-concept work as a forcing function for clarity, not a shortcut, and you know when to stop refining and start sharing results \nYou stay current with emerging architectures, chiplet standards, and system-level design trends, and you bring that perspective into the work without waiting to be asked \nThe Team You'll Be Part Of\nThe System Design Enablement team develops performance models, virtual prototypes, methodologies, and proof-of-concept solutions for next-generation semiconductor systems. Working across hardware, software, and system architecture, the team enables early architecture exploration and system-level decision making for compute-intensive applications in areas such as automotive, robotics, and automation. Its work turns emerging requirements into scalable design approaches, reusable assets, and inputs for product roadmaps.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6487,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Space & Aerospace","EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[],"liveness":{"score":37,"band":"fade","label":"Fading","p_open":1,"p_active":0.676,"p_room":0.55,"age_days":15,"expected_fill_days":11,"reasons":["conf:3","velocity","win:tail","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-engineering-architecture-sr-staff-engineer-18958","json_url":"https://alion.io/job/synopsys-engineering-architecture-sr-staff-engineer-18958.json","meta":{"generated_at":"2026-10-13T02:04:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3133,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-engineering-architecture-sr-staff-engineer-18958"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-engineering-architecture-sr-staff-engineer-18958"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-engineering-architecture-sr-staff-engineer-18958"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-engineering-architecture-sr-staff-engineer-18958\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-engineering-architecture-sr-staff-engineer-18958"}]}